Altera Corporation

Allen K Chan

Wilson Wong

Sergey Yuryevich Shumarayev

Tim Tri Hoang

Weiqi Ding

Thungoc M Tran

Arye Ziklik

Faisal Dada

Vishal Giridharan

Bryon Moyer

Venkat Yadavalli

Karl Lu

Simardeep Maangat

Tin H Lai

Gary Brian Wallichs

Mei Luo

Ali Atesoglu

Syed Reza Bahadur

Samson Tan

Nicholas Sutardja

Kuo-Yin Weng

Receiver circuitry for receiving a data signal includes summation node circuitry that predicts an error value of the received data signal. The receiver circuitry also includes adaptation engine circuitry coupled to the summation node circuitry. The adaptation engine circuitry determines a transmitter adjustment based on the error value and sends a freeze signal to one or more components of the receiver to cause the receiver to continue operating without changing current settings of the one or more components. The receiver circuitry further includes a user interface and sequence controller, coupled to the adaptation engine circuitry, wherein the user interface and sequence controller sends a signal indicative of the transmitter adjustment to the transmitter.

Backchannel transmission adaptation

An integrated circuit may include receiver circuitry that receives data from an external device. Such receiver circuitry may include, among other things, equalization circuitry that may reconstruct the received data before transmitting the received data to other parts of the integrated circuit. The receiver circuitry may include two different equalization circuits. A first equalization circuit may perform equalization on the received data to generate a first equalized output while a second equalization circuit may generate a second equalized output. The receiver circuitry may further include an amplifier circuit that selectively amplifies either the first or second equalized output from the respective first and second equalization circuits based on the data rate of the received data.

Multimode equalization circuitry

Disclosed is a circuit architecture for cancellation of threshold voltage offsets for an array of sense amplifiers. An offset calibration controller, which may be embedded as a hard-wired circuit in the transceiver core circuits, writes the offset adjustment values to a memory-mapped interface circuit. The memory-mapped interface circuit outputs the offset adjustment values to offset adjustment circuits for the sense amplifiers. The offset adjustment circuits may utilize a body bias technique. Advantageously, the disclosed circuit architecture provides for the minimization of residual offset without sacrificing bandwidth. Other embodiments, features and advantages are also disclosed.

Apparatus and method for sense amplifier offset cancellation

One embodiment relates to a method performed by on-die instrumentation. Speculative-high and speculative-low error signals are generated using first and second sense amplifiers. The speculative-high and speculative-low error signals are deserialized to generate speculative-high and speculative-low error data. A subset of bits in the speculation-high and speculation-low error data are determined to be invalid based on prior bits in recovered data obtained using a clock-data recovery and decision feedback equalizer circuit. Another embodiment relates to an integrated circuit with on-die instrumentation for obtaining bit error data for an eye-opening diagram. The integrated circuit includes a voltage multiplexer, a clock multiplexer and first and second sense amplifiers. Other embodiments, aspects and features are also disclosed.

Receiver eye-monitor circuit and method

Systems and methods are described that include adaptation circuitry for processing a data signal. The adaptation circuitry may include summation node circuitry for processing an error value associated with the data signal. The adaptation circuitry may also include adaptation engine circuitry, coupled to the summation node circuitry, for controlling the operation of the summation node circuitry.

Adaptations for partial response summation node embedded FPGA transceiver

A pre-emphasis circuitry that includes (1) a pre-emphasis voltage variation compensation (PVVC) engine having a transition detection circuit and (2) a compensation driver coupled to the PVVC engine is described. In one embodiment, the compensation driver reduces data dependent voltage variations in pre-emphasis provided by the pre-emphasis circuitry. In one embodiment, in response to a predetermined data pattern detected by the PVVC engine, the compensation driver provides an additional boost to performance critical capacitive nodes of the pre-emphasis circuitry. The additional boost causes the performance critical capacitive nodes to charge or discharge more rapidly. In one embodiment, the PVVC engine further includes a digital finite impulse response (FIR) filter coupled to the transition detection circuit. Also, in one embodiment, the PVVC engine further includes an FIR delay circuit coupled to the digital FIR filter and a synchronizer circuit coupled to the digital FIR filter and the FIR delay circuit, where the FIR delay circuit introduces latency to match-delay produced by the transition detection circuit and the synchronizer circuit synchronizes data to be sent to the main driver, the pre-emphasis driver, and the compensation driver.

Pre-emphasis circuitry including a pre-emphasis voltage variation compensation engine

An integrated circuit having transceiver circuitry is provided. The transceiver circuitry may include an equalization circuit such as a decision feedback equalizer (DFE). The DFE may include a variable gain amplifier (VGA) that is coupled to a summation node circuit and a digital sampler. The DFE may also include an operational amplifier that is coupled in a negative feedback loop and that provides a controlled power supply voltage to the VGA so that the VGA is able to provide a stable common mode output voltage to the digital sampler. The operational amplifier may be a self-biased operational amplifier with an output stage that includes miller compensation circuitry for enhanced stability.

Transceiver circuitry with summation node common mode droop reduction

An embodiment of the present invention implements a linear feedback shift register (LFSR) as a counting device for an integrator of a DFE circuit. In embodiments of the present invention, the particular count sequence need not be known, instead only boundary values need be known. For example, for a LFSR having a predetermined count sequence, a digital integrator controller need not know every value of the count sequence. Instead, the digital integrator controller detects predetermined boundary values such as a minimum or maximum count.

Apparatus and method for improved integration circuitry in decision feedback equalization

An integrated circuit includes a duty cycle detection circuit, a comparator circuit, and a tuning circuit. The duty cycle detection circuit receives a clock signal, such as a system clock signal, and detects the level of duty cycle distortion in the clock signal. The comparator circuit then generates an output based on the level of duty cycle distortion that is detected in the clock signal. The tuning circuit may accordingly adjust the clock signal based on the output generated by the comparator circuit to produce an adjusted clock output signal. As an example, the clock output signal produced by the tuning circuit after the adjustment may have a 50% (or significantly close to 50%) duty cycle.

Clock duty cycle calibration circuitry

An integrated circuit is presented. The integrated circuit includes a selection circuit that selects a reference voltage and an output voltage associated with a number of adjustable voltage regulators connected to the selection circuit. The integrated circuit also has an analog to digital converter, which converts the selected output voltage and the reference voltage to a digital representation. An analog state machine of the integrated circuit receives the digital representation from the analog to digital converter and compares the selected output voltage with the reference voltage.

Adjustable voltage regulator calibration circuit

Automatic rate negotiation logic for a high speed serial interface in a programmable logic device determines whether multiple occurrences of a single-bit transition (i.e., a data transition from '0' to '1' to &#x201c;0&#x201d; or from &#x201c;1&#x201d; to &#x201c;0&#x201d; to &#x201c;1&#x201d;) occur within a predetermined time interval on a data channel of a high-speed serial interface. The interval preferably is selected such that multiple occurrences of a single-bit transition mean that the data channel is operating in full-rate mode. The rate negotiation logic may share a phase detector with clock data recovery circuitry in the interface. The phase detector may be a bang-bang phase detector specially adapted to detect single-bit transitions.

Protocol-agnostic automatic rate negotiation for high-speed serial interface in a programmable logic device

One embodiment relates an equalizer which includes a first amplifier stage and a second amplifier stage. The first amplifier stage is configured to apply a first gain at a characteristic frequency while attenuating frequencies in a low frequency range. The second amplifier stage is configured to apply a second gain at the frequencies in the low frequency range. The first amplifier stage may be configured before the second amplifier stage, or vice versa. Another embodiment relates to a method of linear equalization. Another embodiment relates to an amplifier which may be used for linear equalization. Other embodiments, aspects, and features are also disclosed.

Dual-stage continuous-time linear equalizer

The ability of clock and data recovery ('CDR') circuitry on an integrated circuit ('IC') to handle jitter in a serial data input signal can be tested by using transmitter circuitry on the IC to produce a serial data output signal whose time base has been subjected to modulation. Loop-back circuitry on the IC may be used to apply the serial data output signal to the CDR circuitry as the serial data input signal of the CDR circuitry. Modulation circuitry on the IC may be used to cause the above modulation of the time base of the serial data output signal.

Testing performance of clock and data recovery circuitry on an integrated circuit device

One embodiment relates to a method of offset cancellation for a receiver in an integrated circuit. The receiver is set to a phase-detector offset-cancellation mode so as to determine offset cancellation settings for the phase detector. The offset cancellation settings are applied to the phase detector. The receiver is then set to a receiver-driver offset-cancellation mode so as to determine an offset cancellation setting for the receiver driver. This offset cancellation setting is applied to the receiver driver. Another embodiment relates to an integrated circuit configured to perform receiver offset cancellation. The integrated circuit including a receiver driver configured to receive a differential input signal, a phase detector including a plurality of latches, a calibration controller, a voltage source, and first and second pairs of switches. Other embodiments, aspects, and features are also disclosed.

Apparatus and methods of receiver offset calibration

Integrated circuits with decoupling capacitor circuitry are provided. Decoupling capacitor circuitry may include multiple arrays of decoupling capacitors. Each decoupling capacitor array may have a corresponding decoupling capacitor monitoring circuit that is associated with that decoupling capacitor array. Each decoupling capacitor monitoring circuit may include a resistor and switching circuitry. Each decoupling capacitor monitoring circuit may be coupled to a comparator and control circuitry. During testing, the control circuitry may configure each decoupling capacitor array for leakage current testing one at a time. If a decoupling capacitor array is determined to exhibit excessive leakage currents, that decoupling capacitor array will be marked as defective and will be disabled from use. If the decoupling capacitor array is determined to exhibit tolerable leakage currents, that decoupling capacitor array will be enable for use to help reduce power supply noise.

Growing community of inventors

San Jose, CA, United States of America

Allen K Chan