Hewlett-packard Company

Intel Corporation

Apple Inc.

Hewlett-packard Development Company, L.p.

Other

Mill Computing, Inc.

Ruby Bei-loh Lee

Allen J. Baum

Allen Jay Baum

William R Bryg

Ruby B Lee

France Rode

Thomas E Osborne

Peter D Dickinson

Maurice B Steinman

Terrence C Miller

Michael J Mahon

Richard Eugene Kessler

Sanjay Dabral

Theodore Zale Schoenborn

Gregg Alan Bouchard

Sailesh Kottapalli

Tim Frodsham

Rahul R Shah

Peter J Bannon

David Allen Fotland

Scott E Breach

Mohan J Kumar

Robert G Blankenship

Murugasamy K Nachimuthu

Venkatraman Iyer

David Stewart Dunning

Mahesh S Natu

John H Crawford

Naveen Cherukuri

Vedaraman Geetha

Aaron T Spink

Kushagra V Vaid

James R Vash

Sham M Datta

Roger Rawson Godard

Scott P Bobholz

Arthur David Kahlich

William S Worley, Jr

Muraleedhara Herur Navada

Norman Hardy

Jeff Wiedemeier

Chris D Matthews

Peter S Baum

David S Cochran

Russell Kao

Steven S Muchnick

Chung C Tung

Chris C Gianos

Henk Gomarus Caroline Neefs

Ruby Bei-Loh Lee

Davis S Dunning

A computer processing system includes execution logic that generates memory requests that are supplied to a hierarchical memory system. The computer processing system includes a hardware map storing a number of entries associated with corresponding cache lines, where each given entry of the hardware map indicates whether a corresponding cache line i) currently stores valid data in the hierarchical memory system, or ii) does not currently store valid data in hierarchical memory system and should be interpreted as being implicitly zero throughout.

Computer processor employing dedicated hardware mechanism controlling the initialization and invalidation of cache lines

Methods and apparatus relating to repurposing a data lane as a clock lane by migrating to reduced speed link operation are described. In one embodiment, speed of a link is reduced upon detection of failure on a clock lane of the link and one of a plurality of data lanes of a link is repurposed as a replacement clock lane. Other embodiments are also disclosed and claimed.

Repurposing data lane as clock lane by migrating to reduced speed link operation

A technique for performing barrier synchronization among a plurality of program threads. More particularly, at least one embodiment of the invention keeps track of completed tasks associated with a number of program threads using bits within a barrier register that can be updated and reassigned without incurring the amount of bus traffic as in the prior art.

Method and apparatus for communication between two or more processing elements

Methods and apparatus relating to dynamically routing data responses directly to a requesting processor core are described. In one embodiment, data returned in response to a data request is to be directly transmitted to a requesting agent based on information stored in a route back table. Other embodiments are also disclosed.

Dynamically routing data responses directly to requesting processor core

Systems and methods for enabling Reliability, Availability & Serviceability features after launching a secure environment under the control of LaGrande Technology (LT), or comparable security technology, without compromising security are provided. In one embodiment, the method comprises adding at least one specific capability to a processor to enable at least one of CPU hot-plug, CPU migration, CPU hot removal and capacity on demand.

Supporting advanced RAS features in a secured computing system

A method is described in which, in response to notice of a configuration event yet to happen within a network that is part of a link-based computing system, a component within said link based computing system: a) identifies networking configuration information changes to be made by components within the link-based computing system; and, b) sends instances of program code to each one of the components. Each instance of program code is to be executed by a specific component that it was sent to. Each instance of program code is customized to implement the particular one or more networking configuration information changes to be made at the specific component it was sent to.

Live network configuration within a link based computing system

Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.

Methods and apparatuses to effect a variable-width link

A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.

Method and system for response determinism by synchronization

An embodiment of the present invention is a technique to perform error correction using a trial-and-error method. A syndrome generator provides a generation of a data syndrome of a data word modified according to a selection of at least one of error correcting parameters. The data word is associated with at least one transaction performed on a unit. A controller controls iterating the generation of the data syndrome.

Error correction using iterating generation of data syndrome

A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The 'skew' is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.

Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature

A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself. Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The &ldquo;skew&rdquo; is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.

A method and apparatus for instruction prefixing selectively reconfigures certain of the instructions in the microprocessor's instruction set so as to alter the nature of the operation performed by the instruction and/or the designation of operand or result locations accessed by the operation. A prefix instruction is inserted ahead of a 'using' instruction and an operational parameter of the using instruction is modified in accordance with the contents of the prefix instruction. In one application, the prefix instruction may be used to specify a register location for storage of a result of the using instruction's operation or retrieval of an operand. In other applications, the prefix instruction may be used to modify other aspects of instruction execution.

Prefix instruction for modification of a subsequent instruction

A method for reducing interrupt processing overhead is applied in situations when it is not necessary to preserve processor state information. A flag is provided to indicate whether or not the processor is available. Upon recognition of an interrupt, an interrupt vector address is computed based, in part, on the state of the processor available flag. If the processor is available, indicating that it is not currently working on a task, there is no need to preserve the processor state information, and the state-saving portions of the interrupt processing routines are bypassed. On the other hand, if the processor is not available, indicating that the it is engaged in a task, the state information must be preserved so that the processor can return to the task after the interrupt is processed. In this case, the state-saving portions of the interrupt processing routines are not bypassed.

Microprocessor with improved interrupt response with data saving

A method for reducing interrupt processing overhead is applied in situations when it is not necessary to preserve processor state information. A flag is provided to indicate whether or not the processor is available. Upon recognition of an interrupt, an interrupt vector address is computed based, in part, on the state of the processor available flag. If the processor is available, indicating that it is not currently working on a task, there is no need to preserve the processor state information, and the state-saving portions of the interrupt processing routines are bypassed. On the other hand, if the processor is not available, indicating that it is engaged in a task, the state information must be preserved so that the processor can return to the task after the interrupt is processed. In this case, the state-saving portions of the interrupt processing routines are not bypassed.

Microprocessor with improved interrupt response with interrupt data

In a computing system which has memory and an instruction pipeline, a method and apparatus allows for nullification of a second instruction responsive to the state of a nullification field in a first instruction executed prior to the second instruction. After the first instruction is fetched, the operation specified by the first instruction is performed and the results of the operation are stored, including the state of the nullification field. The second instruction is fetched and the operation specified by the second operation is performed. However, conditional upon the state of the nullification field of the first instruction, results, errors, traps and interrupts of the second instruction are not stored in the computer system.

Apparatus and method for nullifying delayed slot instructions in a

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Palo Alto, CA, United States of America

Allen Jay Baum