Monolithic Memories, Inc.

Data General Corporation

Allen H Frederick

Ury Priel

Jerry D Gray

Dale T Trenary

Robert M Whelton

A method of electrically isolating a plurality of semiconductor integrated circuit components and for forming gate elements for silicon gate transistors is disclosed whereby extremely narrow line widths can be formed which heretofore have been unattainable by practicing conventional photolithography.

Retro-etch process for forming gate electrodes of MOS integrated circuits

Shallow, boron implanted regions are formed by ion implanting. Disclosed is a PNP transistor device (lateral type) having a P type emitter region preferably made with a boron implant.

Lateral PNP transistor

Retro-etch process for integrated circuits

This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense amplifier of the memory array are fabricated to have a high resistivity thereby permitting the semiconductor array to operate with much lower power. The high resistivity semiconductor resistors of this write-once, read-only semiconductor memory array are fabricated using an ion implantation step, preferably, between the base and emitter diffusion process steps in fabricating the NPN transistor structures used in the bit line and word line decoders of the memory array. The high resistivity ion implanted resistor regions are preferably shallow, boron implanted regions that are formed by ion implanting through a thin silicon dioxide layer. Various resistor devices are disclosed using shallow, boron implanted, high resistivity regions. Also disclosed are PNP transistor devices (both vertical and lateral types) having P type emitter regions preferably made with a Boron implant. A P-channel MOS device is also disclosed where the P+ source and drain regions are shallow, implanted regions.

High resistivity semiconductor resistor device

Fabrication of high resistivity semiconductor resistors by ion

This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense amplifier of the memory array are fabricated to have a high resistivity thereby permitting the semiconductor array to operate with much lower power. The high resistivity semiconductor resistors of this write-once, read-only semiconductor memory array are fabricated using an ion implantation step, preferably, between the base and emitter diffusion process steps in fabricating the NPN transistor structures used in the bit line and word line decoders or the memory array. The high resistivity ion implanted resistor regions are preferably shallow, boron implanted regions that are formed by ion implanting through a thin silicon dioxide layer. Various resistor devices are disclosed using shallow, boron implanted, high resistivity regions. Also disclosed are PNP transistor devices (both vertical and lateral types) having P type emitter regions preferably made with a boron implant. A P-channel MOS device is also disclosed where the P+ source and drain regions are shallow, implanted regions.

Growing community of inventors

Pacifica, CA, United States of America

Allen H Frederick