Ansys, Inc.

Other

Allen Baker

Ajay Singh Bisht

Renuka Vanukuri

Norman H Chang

Joao Moreno Geada

Deqi Zhu

Lang Lin

Dinesh Kumar Selvakumaran

Preeti Gupta

George Robins

Arti Dwivedi

Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method, performed on a data processing system, can receive input data that contains an RTL representation of a design of a circuit and then determine, from the input data, a set of registers that store security related data during operation of the circuit, wherein the set of registers are a subset of all of the registers in the design. The method then determines, in a simulation of power consumption of the set of registers in the RTL representation, security metrics that indicate a level of potential leakage of security related data such as secret or private cryptographic keys.

Register transfer level based side channel leakage assessment

Systems and methods are provided for calculating a power characteristic of an integrated circuit design. For each standard cell of a gate-level netlist, a path length and a set of attributes are computed. For each leaf-level instance of a register-transfer level (RTL) netlist, a path length and a set of attributes are computed. The standard cells are partitioned into first subsets, each of the first subsets containing standard cells with a same path length and a same set of attributes. For each first subset, a relative percentage for each type of standard cell included in the first subset is calculated. The leaf-level instances are partitioned into second subsets. For each pair of corresponding first and second subsets, standard cells are associated with the leaf-level instances of the second subset based on the relative percentages. A power characteristic of the RTL netlist is calculated based on the associated standard cells.

Systems and methods for estimating a power consumption of a register-transfer level circuit design

An example circuit includes: a first clock gating circuit coupled between a first latch and a second latch and configured to provide a first gated clock signal based at least in part on an input clock signal. The first latch is configured to be activated in response to the first gated clock signal being at a first logic level to pass a data input. The second latch is configured to be activated in response to the input clock signal being at a second logic level to pass a first selection signal.

Systems and methods for reducing power consumption of latch-based circuits

Display screen with a messaging split screen graphical user interface

Display screen portion with graphical user interface

The illustrative embodiments provide a system and method for processing a document. A data storage unit is provided to store data corresponding to the document, several documents processed at a previous time, and a set of rules. A rule in the set of rules may include a rule identifier, a directive to proceed to a second rule based on a condition, a specification of a data component, the specification configured to include a data component identifier, a data component attribute, and a directive to proceed to a second specification of a second data component based on a second condition. A rules-based engine is provided that may communicate with the data storage unit and may execute a rule in the set of rules. The set of rules may include rules for parsing, validating, identifying, relating, selecting, extracting, transforming, generating, analyzing, error correcting, reporting, and sending.

System for processing and using electronic documents

Firearm

Growing community of inventors

San Jose, CA, United States of America

Allen Baker