Advanced Micro Devices Corporation

Allen B Thor

Daniel B Reents

Bruce A Loyer

A universal serial bus (USB) device or host provides a universal serial bus (USB) controller with a direct memory access (DMA) mode. In a DMA mode, a universal serial bus (USB) transmit endpoint may be programmed for a direct memory access (DMA) transmit channel, or a universal serial bus (USB) receive endpoint may be programmed for a direct memory access (DMA) receive channel. For a USB device, a DMA transmit channel performs data transfer to a universal serial bus (USB) host, and a DMA receive channel handles data transfer from the USB host. For a USB host, a DMA transmit channel performs data transfer to the USB device, and a DMA receive channel handles data transfer from the USB device. A universal serial bus transmit protocol and a universal serial bus receive protocol for the DMA mode of the USB controller permit a maximum packet size of universal serial bus (USB) data to be programmed to a value greater than the physical size of a USB transmit or receive buffer of a USB transmit or receive endpoint. A USB controller with a DMA mode thus allows for a significant reduction in the buffer size of a USB transmit or receive buffer. A USB device having a controller with a DMA mode handles USB data as fast as the USB host can request USB data.

Universal serial bus controller with a direct memory access mode

A system for controlling a clock rate of a microprocessor which includes a core clock operatively coupled to the processor, the core clock providing the microprocessor with a core clock signal for clocking the processor. A power supply operatively coupled to the microprocessor provides power to the processor. An intelligent clock generating system provides the core clock with at least one clock signal of a plurality of clock signals to be used as the core clock signal, wherein the plurality of clock signals includes a master clock signal and at least one ramped clock signal.

System and method to control microprocessor startup to reduce power

Exchangeable LID modules are provided to enable the frame relay switching system to be interfaced to a specific data terminal, for example, synchronous, asynchronous terminals or T1 line, by performing on the receive side the physical translation of information on the input lines to clock signal CLK and HDLC framed data. On the transmit side, the HDLC framed data and clock signal CLK are translated into the data appropriate for a data terminal. The type of the translation is specific to the line to be interfaced with. To support a synchronous data terminal, a synchronous receiver is provided that extracts valid data patterns from a synchronous data stream. The data patterns are replaced with the data stream of appropriate levels when data are transmitted. When data are received from a T1 line, the LID splits the received data stream into user data and signalling data. The signalling data are buffered to form a signalling frame sent to a signalling frame relay packet management device (FRYPAM) separate from a user data FRYPAM that receives user data frames. To support an asynchronous data terminal, a microprocessor is provided to handle PAD and LAPB operations for transforming asynchronous data into X.25 format.

Line interface device for fast-packet switching network

In a fast-packet network, incoming high-level data-link control (HDLC) data are supplied by a receiving line interface device to a packet management device comprising a receiving state machine that shifts the data through a data link connection identifier (DLCI) extractor. The extracted DLCI is used as an address indicating a location of a translation RAM that stores the destination DLCI and control data corresponding to the incoming HDLC data. The destination DLCI replaces the current DLCI field of the incoming data. A frame control state machine requests a frame buffer of a frame buffer RAM to be allocated to the incoming HDLC packet and writes the data to the allocated buffer. Simultaneously, a packet availability message is sent to the destination packet management device indicated by the control data in the translation RAM. A transmitting circuit of the destination packet management device has a transmitting state machine that rewrites the HDLC data from the frame buffer RAM to a FIFO register. When the FIFO register is full or entire data frame is in the FIFO register, the data are transferred to an HDLC transmitter coupled to a transmitting line interface device.

Packet management device for fast-packet network

A modular architecture for fast-packet networks that comprises line interface devices (LIDs) exchangeable to support numerous line interfaces. The LIDs supply frame relay packet management devices (FRYPAMs) with unified framed data in high-level data-link control (HDLC) format and clock signals. The receiving FRYPAMs perform cyclic redundancy check (CRC) checking, check look-up tables to convert the data link connection identifier (DLCI) fields if needed, write the received frames with correct frame check sequence (FCS) fields into a frame buffer RAM and communicate with other FRYPAMs to update transmission queues. The transmitting FRYPAMs read the frames from the frame buffer RAM and send them to the transmitting LIDs coupled to destination end points. The transmitting LIDs convert the HDLC data from the FRYPAMs to the format appropriate for the specific line interface and transmit the information to the destination end points. A frame buffer manager allocates available frame buffers in the frame buffer RAM among the FRYPAMs. A control and maintenance processor handles control and maintenance operations for the fast-packet network. It updates the look-up tables and communicates DLCI and line interface parameters to the LIDs in real time.

Modular architecture for fast-packet network

A communication system transmits and receives encrypted digital signal samples. The system includes a generator for generating digital signal samples to be encrypted and an encryption memory for storing the encrypted digital signal samples. The digital signal samples address the encryption memory which provides the encrypted digital signal samples responsive to the digital signal samples. The system further includes a transmitter for transmitting the encrypted digital signal samples and a receiver for receiving the encrypted digital signal samples. The system further includes a decryption memory for storing the digital signal samples at storage locations complimentary to the encrypted digital signal sample storage locations of the encryption memory. The encrypted digital signal samples address the decryption memory to cause the decryption memory to provide the digital signal samples responsive to the encrypted digital signal samples for reproducing the original digital signal samples.

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Livingston, NJ, United States of America

Allen B Thor