Cree Gmbh

Allan Ward

Jason Patrick Henning

Helmut Hagleitner

Scott Thomas Sheppard

Saptharishi Sriram

Alexander V Suvorov

Scott Thomas Allen

Richard Peter Smith

Zoltan Ring

Andrew K Mackenzie

Sei-Hyung Ryu

Anant Kumar Agarwal

Keith Dennis Wieber

An edge termination structure for a silicon carbide semiconductor device includes a plurality of spaced apart concentric floating guard rings in a silicon carbide layer that at least partially surround a silicon carbide-based junction, an insulating layer on the floating guard rings, and a silicon carbide surface charge compensation region between the floating guard rings and adjacent the surface of the silicon carbide layer. A silicon nitride layer is on the silicon carbide layer, and an organic protective layer is on the silicon nitride layer. An oxide layer may be between the silicon nitride layer and the surface of the silicon carbide layer. Methods of forming edge termination structures are also disclosed.

Edge termination structures for silicon carbide devices

A semiconductor device structure is disclosed that includes a wide-bandgap semiconductor portion selected from the group consisting of silicon carbide and the Group III nitrides. An interconnect structure is made to the semiconductor portion, and the interconnect structure includes at least two diffusion barrier layers alternating with two respective high electrical conductivity layers. The diffusion barrier layers have a coefficient of thermal expansion different from and lower than the coefficient of thermal expansion of the high electrical conductivity layers. The difference in the respective coefficients of thermal expansions are large enough to constrain the expansion of the high conductivity layers but less than a difference that would create a strain between adjacent layers that would exceed the bond strength between the layers.

Metallization structure for high power microelectronic devices

A MESFET includes a silicon carbide layer, spaced apart source and drain regions in the silicon carbide layer, a channel region positioned within the silicon carbide layer between the source and drain regions and doped with implanted dopants, and a gate contact on the silicon carbide layer. Methods of forming a MESFET include providing a layer of silicon carbide, forming spaced apart source and drain regions in the silicon carbide layer, implanting impurity atoms to form a channel region between the source and drain regions, annealing the implanted impurity atoms, and forming a gate contact on the silicon carbide layer.

Transistors having implanted channel layers and methods of fabricating the same

Fabrication of a Schottky diodes may include providing a Schottky contact layer containing a low barrier metal layer with spaced apart high barrier metal islands therein on a first surface of a substrate. A diode contact is formed on a second surface of the substrate that is opposite to the first surface. Formation of the Schottky contact layer may include providing a liquid mixture of a high barrier metal and a low barrier metal on the first surface of the substrate. Temperature and/or relative concentrations of the high and low barrier metals in the liquid mixture may be controlled to cause regions of the high barrier metal to solidify within the liquid mixture and agglomerate to form the spaced apart high barrier metal islands while inhibiting solidification of the low barrier metal. The temperature and relative concentrations may then be controlled to cause the low barrier metal to solidify and form the low barrier metal layer containing the high barrier metal islands.

Schottky diodes containing high barrier metal islands in a low barrier metal layer and methods of forming the same

A unit cell of a metal-semiconductor field-effect transistor (MESFET) includes a semi-insulating substrate having a surface, an implanted n-type channel region in the substrate, and implanted source and drain regions extending from the surface of the substrate into the implanted channel region. A gate contact is between the source and the drain regions, and an implanted p-type region is beneath the source region. The implanted p-type region has an end that extends towards the drain region, is spaced apart vertically from the implanted channel layer, and is electrically coupled to the source region. Methods of forming transistors including implanted channels and implanted p-type regions beneath the source region are also disclosed.

Transistors having implanted channels and implanted P-type regions beneath the source region

A method of producing an ohmic contact and a resulting ohmic contact structure are disclosed. The method includes the steps of forming a deposited film of nickel and silicon on a silicon carbide surface at a temperature below which either element will react with silicon carbide and in respective proportions so that the atomic fraction of silicon in the deposited film is greater than the atomic fraction of nickel, and heating the deposited film of nickel and silicon to a temperature at which nickel-silicon compounds will form with an atomic fraction of silicon greater than the atomic fraction of nickel but below the temperature at which either element will react with silicon carbide. The method can further include the step of annealing the nickel-silicon compound to a temperature higher than the heating temperature for the deposited film, and within a region of the phase diagram at which free carbon does not exist.

Silicon-rich nickel-silicide ohmic contacts for SiC semiconductor devices

A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.

Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides

A semiconductor device is disclosed that includes a contact and an adjacent film on the surface of an underlying doped semiconductor material. The film has sufficient fixed charge to create an inversion layer adjacent the surface of the doped semiconductor material that under depletion conditions at least balances the number of surface states at the doping concentration of the underlying semiconductor material.

Reduced leakage power devices by inversion layer surface passivation

An improved termination structure for high field semiconductor devices in silicon carbide is disclosed. The termination structure includes a silicon carbide-based device for high-field operation, an active region in the device, an edge termination passivation for the active region, in which the edge termination passivation includes, an oxide layer on at least some of the silicon carbide portions of the device for satisfying surface states and lowering interface density, a non-stoichiometric layer of silicon nitride on the oxide layer for avoiding the incorporation of hydrogen and for reducing parasitic capacitance and minimizing trapping, and, a stoichiometric layer of silicon nitride on the nonstoichiometric layer for encapsulating the nonstoichiometric layer and the oxide layer.

Growing community of inventors

Durham, NC, United States of America

Allan Ward