Lattice Semiconductor Corporation

Altera Corporation

Allan Thomas Davidson

Satwant Singh

Ju Shen

Cyrus Y Tsui

Albert L Chan

Michael Menghui Zheng

Neville Carvalho

Sergey Yuryevich Shumarayev

Bruce B Pedersen

David Wolk Mendel

Tim Tri Hoang

Jinghui Zhu

Kumara Tharmalingam

Andy Turudic

Marwan A Khalaf

Kalyan Kankipati

Seungmyon Park

Daniel Bowersox

Shari L Mann

A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

Transceiver system with reduced latency uncertainty

A digital phase detector circuit and corresponding monitor and control logic is presented. The digital phase detector has two storage elements, where the data input of the first storage element receives a first clock signal and the data input of the second storage element receives a second clock signal. A time shifter shifts the second clock signal by a shift period, and transmits the shifted signal to the clock input of the storage elements. The signals applied to the data inputs are transmitted from the storage elements when the clock input receives the shifted second clock signal from the time shifter. A monitor and control module samples the data output from the storage elements after each shifted second clock signal is transmitted by the time shifter. The sampling of the output data provides the data used to determine the time relationship between the first and the second clock signals.

Digital phase detection circuit and method

In one embodiment, a circuit is provided that includes: a differential input receiver having a first input terminal and a second input terminal; a first programmable switch coupled to the first input terminal and coupled through a first resistor to a first voltage such that if the first programmable switch is closed, the first input terminal is pulled towards the first voltage; and a second programmable switch coupled to the second input terminal and coupled through a second resistor to a second voltage such that if the second programmable switch is closed, the second input terminal is pulled towards the second voltage, wherein the first and second programmable switches are programmed to be closed during a differential input mode of operation in which the differential input receiver processes differential input signals provided to the first and second input terminals.

Differential input receiver with programmable failsafe

Systems and methods are disclosed for providing output impedance measurement techniques. For example, in accordance with an embodiment of the present invention, a system includes a controller adapted to measure an output impedance of a first circuit that provides an output signal having a first voltage level. The output signal from the first circuit is compared to a plurality of voltage levels provided by the controller, with the controller determining the output impedance of the first circuit based on the results of the comparison.

Output impedance measurement techniques

An architecture is disclosed to provide high-speed input/output interface capabilities for programmable devices. One or more configurable input/output circuits are situated between the input/output drivers and the programmable core circuitry of the programmable device. The input/output circuits are optimized for the high-speed requirements of the input/output interface standards, with each input/output circuit configurable to support numerous, different input/output interface standards. The programmable core circuitry may be utilized to support the lower-speed requirements of the input/output interface standards.

Scalable device architecture for high-speed interfaces

Systems and methods are disclosed for programmable logic devices requiring a high-speed input/output interface. Hard-macro circuits that are configurable, scalable, and cascadable complement the input/output drivers and the programmable core logic of the programmable logic device. The hard-macro circuits are permanent, high-speed logic circuits that are optimized for the performance requirements of high-speed input/output interface standards. High-speed memory interfaces, clock and data recovery interface standards, source-synchronous interface standards, and system-synchronous interface standards may be supported by the hard-macro circuits.

Programmable and fixed logic circuitry for high-speed interfaces

A family of related programmable logic devices is provided. The family includes a first programmable logic device having n number of logic modules. The first programmable logic device is incorporated into a first package, with the n number of logic modules bonded out to the first package. A second programmable logic device has a number of logic modules greater than n. The second programmable logic device is incorporated into a second package of substantially the same size as the first package and having an identical pin assignment, with only n number of the logic modules of the second programmable logic device bonded out to the second package.

Package migration for related programmable logic devices

A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portion of the programmable logic device.

Combination of global clock and localized clocks

A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portions of the programmable logic device.

Growing community of inventors

San Jose, CA, United States of America

Allan Thomas Davidson