Texas Instruments Corporation

Other

Dallas Semiconductor Corporation

Allan T Mitchell

Howard L Tigelaar

Agerico L Esquivel

Bert R Riemenschneider

Imran Khan

James L Paterson

Keith M Jarreau

Mark Eskew

Kalipatnam V Rao

Michael A Wu

Weidong Tian

Clarence W Teng

Kaiping Liu

Harvey J Stiegler

Shanjen “Robert” Pan

Shaym G Garg

Thomas E Harrington, Iii

Robert N Rountree

Shanjen Pan

Jack G Qian

Roy Austin Hensley

David A Helsley

Howard L Tigilaar

Tanmay Kumar

Varun Singh

An atmometer system based on an analog floating-gate structure and circuit. The floating-gate circuit includes a floating-gate electrode that serves as a gate electrode for a transistor and a plate of a storage capacitor. A conductor element exposed at the surface of the integrated circuit is electrically connected to the floating-gate electrode; reference conductor elements biased to ground are also at the surface of the integrated circuit. In operation, the transistor is biased and moisture is dispensed at the surface. The drain current of the transistor changes as the floating-gate electrode discharges via the surface conductors and a conduction path presented by the moisture. The elapsed time until the drain current stabilizes indicates the evaporation rate.

Analog floating-gate atmometer

An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.

Ultraviolet energy shield for non-volatile charge storage memory

In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

Non-volatile anti-fuse with consistent rupture

An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Analog floating-gate memory manufacturing process implementing n-channel and p-channel MOS transistors

Analog floating-gate memory with N-channel and P-channel MOS transistors

An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIG.) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (), an access transistor (), and a sense transistor (). A current path of each access transistor is connected in series with a current path of each respective sense transistor. A first program data lead () is connected to the switch of each memory cell in a first column. A bit line () is connected to the current path of each access transistor in the first column. A read select lead () is connected to a control terminal of each access transistor in the first row. A first row select lead () is connected to a control terminal of the switch in each memory cell in a first row.

Array architecture for reduced voltage, low power, single poly EEPROM

An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Low leakage capacitor for analog floating-gate integrated circuits

An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.

Unitary floating-gate electrode with both N-type and P-type gates

A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (I) results from the fluorine implant.

On current in one-time-programmable memory cells

Current in one-time-programmable memory cells

An analog floating gate circuit (--) includes a first sense transistor (), a first storage capacitor (), and first () and second (A,) tunneling regions. Various portions of a first floating gate conductor () form a floating gate of the first sense transistor, a floating first plate of the first storage capacitor (), a floating first plate of the first tunneling region, and a floating first plate of the second tunneling region, respectively. A second plate of the first storage capacitor is coupled to a first reference voltage (V, GND), and a second plate of the second tunneling region is coupled to a second reference voltage (V/GND). Compensation circuitry (--) is coupled to the first floating gate conductor, for compensating loss of trapped charge from the first floating gate conductor.

Analog floating gate charge loss compensation circuitry and method

Growing community of inventors

Heath, TX, United States of America

Allan T Mitchell