International Business Machines Corporation

Cadence Design Systems, Inc.

Allan Robert Bertolet

Scott Whitney Gould

Terrance John Zittritsch

Kim P Clinton

Timothy Shawn Reny

Frank Ray Keyser, Iii

Brian A Worth

Eric Ernest Millham

Joseph Andrew Iadanza

Steven Paul Hartman

Christine Marie Fuller

Gulson Yasar

Albert Manhee Chu

James Fiore

Frank David Ferraiolo

Larry Wissel

William R Griffin

Kenneth Ferguson

Samuel K Weinstein

Eberhard B Gramatzki

Frank Ray Keyser Iii

Ronald Raymond Palmer

John G Petrovick, Jr

Eberhard Gramatski

A method of fabrication are provided in which permanent external electrical connection to active circuitry in a semiconductor structure can be made through either a wire bond pad or metal bump formed thereon. A final metallization including a wire bond pad is disposed over and electrically connected with the active circuitry. An insulating material film is disposed over the final metallization leaving the wire bond pad and a portion of the final metallization laterally displaced from the pad exposed. A metal bump contacts the laterally displayed exposed portion of the final metallization. The wire bond pad is electrically coupled with and laterally displaced from the metal bump through the final metallization. The metal bump and wire bond pad are configured to facilitate electrical connection of the semiconductor structure with an external connector, such as a modular packaging substrate. The structure may also be used for testing and burning in a semiconductor die without direct physical contact of the external testing device to the wire bond pad.

Chip design process for wire bond and flip-chip package

A glitch free delay line multiplexing technique is described that includes an intermediate multiplexing system and an output multiplexer. The intermediate multiplexing system receives signals from a plurality of delay units and outputs a subset of delay signals that includes the signal presently selected, the signal presently selected with an additional delay, and the signal presently selected with one less delay. The intermediate multiplexing system receives a control word from a select mechanism in a non-time critical manner. The output multiplexer receives the least significant bits of the control word and outputs the selected signal.

Glitch free delay line multiplexing technique

A method and system for defining, placing and routing kernels for a family of integrated circuits is provided. The integrated circuits are defined using repeatable row and column circuit types. Kernels are defined by the intersections of the row and column circuit types in the array. The kernels are placed and routed automatically for each member of the family of integrated circuit arrays, each member being generally characterized by a different size, i.e., a different number of repeatable row or column circuit types.

Method and system for layout and schematic generation for heterogeneous

A semiconductor structure and method of fabrication are provided in which permanent external electrical connection to active circuitry in the structure can be made through either a wire bond pad or metal bump formed thereon. A final metallization including a wire bond pad is disposed over and electrically connected with the active circuitry. An insulating material film is disposed over the final metallization leaving the wire bond pad and a portion of the final metallization laterally displaced from the pad exposed. A metal bump contacts the laterally displaced exposed portion of the final metallization. The wire bond pad is electrically coupled with and laterally displaced from the metal bump through the final metallization. The metal bump and wire bond pad are configured to facilitate electrical connection of the semiconductor structure with an external connector, such as a modular packaging substrate. The structure may also be used for testing and burning in a semiconductor die without direct physical contact of the external testing device to the wire bond pad.

Consolidated chip design for wire bond and flip-chip package technologies

A programmable logic cell has four cell input nodes and a plurality of combinational logic circuits. Four inverter circuits are provided for programmably inverting respective input logic signals, each inverter circuit having an inverter input node connected to a respective cell input node for accepting its respective input logic signal therefrom. Each inverter is programmable into a first state wherein a logic signal representing the complement of the input logic signal is provided to the inverter output node, and a second state wherein a logic signal representing the non-complement of the input logic signal is provided to the inverter output node. The inverter circuits buffer their input logic signals in both their first and second states. A first logic gate of the plurality of combinational logic circuits has first and second inputs each connected to a respective output node of one of two of the four inverter circuits, and a second logic gate has first and second inputs each connected to a respective output node of one of the other two of the four inverter circuits. The inverter circuits may be implemented as XNOR gates.

Programmable inverter circuit used in a programmable logic cell

A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g., clock) input available to at least one of the input multiplexers; a flip-flop connected within the logic cell; and internal cell feedback. The preferred method of programming utilizes user-programmed SRAM memory cells.

Programmable logic cell

A programmable array having programmable logic cells, a programmable interconnect network and a programmable I/O system. Two I/O interfaces are provided for respective logic cells about the perimeter of the array. The I/O interfaces comprise input, output and enable paths. Each of these paths has an associated multiplexer. An I/O routing network is positioned about the perimeter of the array. Conductors connecting the I/O interface multiplexers to the programmable interconnect network also intersect, and can be programmably connected to, buses of the I/O routing network.

Programmable array I/O-routing resource

Programmable logic cell having configurable gates and multiplexers

Cascode voltage switch (CVS) logic circuits include a CMOS logic tree having multiple logic branches and a bipolar, branch isolation transistor. Each logic branch of the logic tree changes state between a logic '1' and a logic '0', with a state change being manifested as a charging or discharging of the logic branch. The bipolar transistor comprises a multiple-emitter bipolar transistor wherein each emitter is electrically coupled to a different logic branch of the CMOS logic tree. A precharge circuit, coupled to the logic tree via the bipolar transistor, provides charge to an output of the CVS circuit prior to operation of said logic tree. The logic branches of the logic tree are charged and discharged substantially independently of one another thereby enhancing speed of the combinatorial logic circuit. Various circuit modifications and generalizations are also discussed.

Branch isolation circuit for cascode voltage switch logic

Growing community of inventors

Williston, VT, United States of America

Allan Robert Bertolet