Advanced Micro Devices Corporation

Spansion Llc.

Allan Parker

Joseph C Skrovan

Arthur Benjamin Oliver

Gregory Charles Yancey

Sean Michael O'Mullan

Bradley Edman Sundahl

Joseph Kucera

John Anthony Darilek

Edward V Bautista, Jr

Tat Hin Tan

Matthew Ronald Croft

Jackson Huang

Ali Pourkeramati

Bryan William Hancock

Pedro A Sanchez

Ed Bautista

Tan Tat Hin

Murni Mohd-salleh

Glen Lam

Brett Gerhardt

A method, apparatus, and manufacture for a memory device is provided. The memory device includes a memory cell region including sectors, where each sector includes memory cells. The memory device further includes a memory controller that is configured to control program operations and erase operations to the memory cells. During erase operations to the memory cells, pre-programming occurs in which each un-programmed memory cell in the sector being erased is programmed by applying at least one programming pulse at a program voltage until a program verify passes. Then, the program voltage is adjusted based on the number of programming pulses applied until the program-verify passed. During subsequent program operations in that sector, programming pulses are applied with the adjusted program voltage.

Method, apparatus, and manufacture for flash memory adaptive algorithm

An electronic device includes an input/output (I/O) interface and a plurality of memory elements comprising a non-volatile memory portion for storing a default firmware and a working memory portion having a firmware area. The device also includes a controller coupled to the I/O interface and the memory elements, where the controller is configured for operating the memory elements, according to the firmware area, and for monitoring the I/O interface. In the device, the controller is also configured for loading the default firmware into the firmware area when the controller is enabled and for granting access to the firmware area for loading an alternate firmware if a bypass code is detected at the I/O interface.

Field upgradable firmware for electronic devices

A memory module is provided. The memory module includes die packages and a charge pump that is external the die packages. Each die package includes a flash memory device, and each of the flash memory devices includes bit lines and memory cells coupled to the bit lines. The charge pump provides a charge pump voltage that is selectively provided to the bit lines in each flash memory device in each of the die packages.

Apparatus and method for external charge pump on flash memory module

A method and apparatus for a memory device is provided. The memory device includes a memory cell, a memory controller, and a temperature-sensing device that detects a temperature. The memory controller enables adjusting, based on the detected temperature, a parameter associated with a bit-altering operation to the memory cell that changes a threshold voltage of the memory cell such that the threshold voltage to which the memory cell is changed to by the bit-altering operation is compensated for variations in temperature.

Method and apparatus for temperature compensation for programming and erase distributions in a flash memory

A method, apparatus, and manufacture for a memory device is provided. The memory device includes memory cells that each store two bits, and a memory controller. During write operations, for each bit in each memory cell that is to be programmed, the memory controller determines whether both bits of the memory cell are being programmed. While controlling an application of programming pulses to the memory cell to program the bit, if both bits of the memory cell are being programmed, the memory controller causes the application of each programming pulse to the bit to occur for a reduced duration. Otherwise, the memory controller causes the application of each programming pulse to the bit to occur for a standard duration. The reduced duration is less than three-fourths of the standard duration.

Method, apparatus, and manufacture for flash memory write algorithm for fast bits

An electronic device is provided including an input/output (I/O) interface, a plurality of memory elements, a controller coupled to the I/O interface and the plurality of memory elements. In the device, the controller configured for operating the plurality of memory elements during a normal operating mode of the electronic device, where responsive to receiving a command for replacing a selected memory sector in the electronic device during the normal operating mode, the controller is configured for identifying one or more available spare memory sectors in the electronic device and modifying at least one memory map in the electronic device to replace the selected memory sector with the one of the available spare memory sectors.

Field programmable redundant memory for electronic devices

Systems () and methods () for reading data from a memory device (). The methods involve () receiving first read request signals () for first data stored in the memory device. In response to the first read request signals, () retrieving a first page of data from a cell array () of the memory device. The methods also involve () receiving second read request signals for second data stored in the memory device. () Next, a determination is made as to whether at least a portion of a memory address for the second data is the same as at least a respective portion of a memory address for the first data. () If it is determined that the respective portions of the memory addresses are the same, then a read access to the cell array is disabled.

Memory device

Systems and/or methods that facilitate error correction of data are presented. An error correction code (ECC) control component facilitates enabling or disabling error correction of data being written to or read from memory, such as flash memory, based on ECC indicator data associated with a piece of data. The ECC control component can analyze data, parity code, and/or indicator data associated with the incoming data and/or data stored in the memory location where the incoming data is to be written to determine whether parity code can be written for the incoming data and/or whether error correction can be enabled with respect to the incoming data. Error correction can be enabled when an indicator bit associated with the data is unprogrammed (e.g., bit set to '1' state) and can be disabled by programming the indicator bit (e.g., bit set to a '0' state).

Error correction coding in flash memory devices

Methods for recycling unused error correction code (ECC) during flash memory programming, comprise generating ECC from user data to form a syndrome and storing the syndrome into volatile memory. ECC is re-encoded corresponding to the syndrome read from the memory with new user data. Re-encoding ECC comprises comparing new ECC with the most recent ECC of the previous syndrome, correcting a bit error in the new ECC, and indicating if the new ECC has failed.

Implementation of recycling unused ECC parity bits during flash memory programming

Flash memory systems and methods for facilitating a single logical cell erasure in a flash memory device whereby logical cell mapping is changed from using a single physical cell to using pair physical cells, thereby creating a single program and erase entity as a single logical cell. By mapping two adjacent physical cells as a single logical cell, the flash memory device can be programmed and erased on a single bit or variable bit length basis with conventional technologies. Various operations can be performed on a flash device on a basis of the single program and erase entity.

Flash mirror bit architecture using single program and erase entity as logical cell

Aspects describe a system and method for using a high voltage state as an erase condition in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a single logical cell, thereby creating a single program and erase entity. Logical cell erase, program, and/or read can be accomplished by using two channel regions in union. This combination can allow for single logical cell erasure in a flash device and the use of a high voltage state as an erased state. A default erased state can be a high voltage state. As a result, program operations can be performed by changing a voltage state of the single program and erase entity to a low voltage state, and erase operations can be performed by changing a voltage state of the single program and erase entity to a high voltage state.

High VT state used as erase condition in trap based nor flash cell design

Flash memory systems and methodologies are provided herein for facilitating single logical cell erasure and quad or more bit storage in a flash device. The single logical cell erasure can be accomplished by employing a single program and erase entity as a single logical cell. The single program and erase entity is a combination of neighboring drain/source regions of two adjacent physical memory cells. By mapping two adjacent physical cells as a single logical cell, the flash memory device can be programmed and erased on a single bit or variable bit length basis. The memory cells can contain four or more data states, and each of the two adjacent memory cells in the single program and erase entity can be programmed independently from each other. As a result, the single program and erase entity can store four or more bits.

Quad+bit storage in trap based flash design using single program and erase entity as logical cell

Flash memory systems and methodologies are provided for providing multiple virtual ground decoding schemes in a flash device. The flash device can include sector configure registers for selecting a specific ground scheme at sector level. The sector configure registers can select a decoding scheme from multiple virtual ground decoding schemes including a conventional dual bit decoding scheme and a single program and erase entity decoding scheme. Since the single program and erase entity decoding scheme can emulate EEPROM functionality in a flash device, the combination of the conventional dual bit decoding scheme and the single program and erase entity decoding scheme can provide both dual bit high density storage and EEPROM emulation in a single flash device.

Sector configure registers for a flash device generating multiple virtual ground decoding schemes

Flash memory systems and methodologies are provided herein for providing byte alterability in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a logical cell for emulating byte alterability. By mapping two adjacent physical cells as a single logical cell, the logical cell is a combination of neighboring drain/source regions, thereby creating a single program and erase entity. The single program and erase entities can allow for logical cell erase and program in either direction of a low voltage state or a high voltage state on a single bit or variable bit length basis. By employing the single program and erase entity, the subject innovation can provide a cost-effective approach to emulating electrically EEPROM in a flash device.

EEPROM emulation in flash device

Flash memory systems and methodologies are provided herein for facilitating a single logical cell erasure and dynamic erase state. The single logical cell erasure can be accomplished on a basis of a single program and erase entity which is a combination of neighboring drain/source regions of two adjacent physical memory cells. The dynamic erase state can involve an indicator bit that indicates an erase direction of a low voltage state or a high voltage state. The single logical cell erasure can be performed by changing a voltage state of a single program and erase entity according to the indicated erase direction. By employing the indicator bit with the single program and erase entity decoding scheme, the methods and systems can reduce erase time and/or a number of cycles, thereby increasing system reliability, efficiency, and/or durability.

Growing community of inventors

Austin, TX, United States of America

Allan Parker