International Business Machines Corporation

Allan L Mullgrav, Jr

John D Davis

Michael Anthony Sorna

Joseph M Mosley

John Farley Ewen

Allan Harvey Dansky

Edward F Culican

Philip E Pritzlaff, Jr

Clarence I Peterson, Jr

Philip F Noto

Scott A Mc Cabe

A power supply noise compensation amplifier has an input for connection to a power supply. The amplifier includes a differential amplifier circuit for providing an instantaneous amplified signal in response to power supply noise, and produces an output signal with an instantaneous opposite polarity from the power supply noise so a noise sensitive circuit connected to the noise compensation amplifier has a compensated power supply signal which enables it to produce a reduction in the amplitude of the noise signal at the output thereof. The differential amplifier circuit includes a differential pair of coupled transistor circuits including a leading transistor circuit and a lagging transistor circuit. The leading and lagging transistor circuits have source-drain circuits connected in parallel to the source-drain circuit of a constant current transistor so the leading and lagging transistor circuits must share a common current as a function of voltages on the leading node connected to the gate of the leading transistor and a lagging node connected to the gate of the lagging transistor. The leading transistor circuit includes a first FET transistor having leading node connected to both and the gate electrode thereof and a resistive circuit. The lagging transistor circuit includes a lagging FET transistor having a lagging node connected to both the gate electrode thereof and the resistive and capacitive elements, and the differential amplifier circuit includes a differential pair of coupled transistor circuits including a leading transistor circuit and a lagging transistor circuit.

Power supply noise compensation amplifier

A voltage controlled oscillator of a phase locked loop circuit having digitally controlled gain compensation. The digital control circuitry provides binary logic input to the voltage controlled oscillator for a digitally controlled variable resistance circuit, a digitally controlled variable current transconductor circuit, or differential transistor pairs having mirrored circuitry for adjusting the V-I gain. The latter configuration requires the voltage controlled oscillator to incorporate a source-coupled differential pair which is driven by a low pass filter capacitor output voltage, and connected to load transistors; a current source and a current mirror for generating a tail current; individual banks of transistors to mirror the load transistor currents; a digital-to-analog converter with control lines outputted there from, the digital-to-analog converter used to increase the amount of current allowed to flow to the transconductor output, the current being digitally increased and decreased corresponding to an amount of current pulled from the current source, and mirroring the current through at least one transistor mirror circuit.

Linear voltage controlled oscillator transconductor with gain compensation

A highly stable, high frequency voltage controlled oscillator (VCO) for phase locked loops is adapted to be fully integrated on a single silicon chip and is operable over a wide frequency range without using off-chip capacitors. The VCO is a fully differential ring oscillator with fully differential voltage control. The VCO is constructed from basic blocks made of differential emitter coupled transistor pairs. Voltage control is provided by differential d.c. amplifiers which vary the capacitive load seen by the logic blocks.

Integrated differential voltage controlled ring oscillator

A push-pull driver circuit operative with two input logic signals of opposite sense has a first bipolar transistor with a base terminal connected to a first input signal, and an emitter terminal connected to a second bipolar transistor which takes the place of the emitter resistor in the usual construction of an emitter follower circuit. During an activation of the first transistor to pass current, this being the pull-up stage, the second transistor is in a quiescent state to develop a voltage drop provided by current flow from the first transistor. A current mirror maintains a small quiescent current in the second transistor so that it can be activated rapidly upon occurrence of the pull-down transition. During a deactivation of the first transistor to terminate current flow in the first transistor, the voltage drop across the second transistor decreases, this being the pull-down stage. The voltage drop across the second transistor serves as an output signal of the driver circuit. During the pull down stage, the second transistor is activated momentarily via the capacitance of a back-biased transistor to pass current for rapid reduction of the voltage drop across the second transistor, this being in response to the second input signal. To avoid placing the second transistor in a state of saturation, a bypass transistor is connected across the base-collector terminal of the second transistor in the reverse direction of current flow in the second transistor to prevent the development of excessive base drive to the second transistor.

Low power push-pull driver

A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

Analog macro embedded in a digital gate array

An oscillator with noise rejection and a fifty percent duty cycle for the on-chip generation and conversion of a sine wave to a square wave, using an external reference crystal. The circuit comprises a low gain current switch including a first and second switching transistors, with the control lines of the switching transistors connected to a reference voltage line. The reference crystal is connected across the control input and the current receiving terminals of the first transistor so that a square wave is obtained at the current receiving terminal of the second transistor. A threshold circuit is included for adjusting the voltage of the square wave signal from the second transistor and applying the adjusted signal to a diode-coupled receiver circuit, which provides the output for the circuit. This oscillator circuit provides a double action noise immunity through the use of a low gain current switch to prevent noise amplification, in combination with a diode-coupled receiver which is affected by noise only during signal transitions. A duty cycle very close to fifty percent is realized by the circuit.

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Wappingers Falls, NY, United States of America

Allan L Mullgrav, Jr