Arm Limited

Allan John Skillman

Antony John Penton

Peter Richard Greenhalgh

Simon John Craske

Ian Michael Caulfield

Max John Batley

Chiloda Ashan Senerath Pathirane

Vladimir Vasekin

Andrew Christopher Rose

Jean-Baptiste Brelot

Peter Vrabel

Max Zardini

Daniel Paul Schostak

An apparatushas a processing pipelinesupporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structureis accessible in both the first and second processing modes. When the second processing mode is selected, control circuitrytriggers a subsetof the entries of the storage structure to be placed in a power saving state.

Processing pipeline with first and second processing modes having different performance or energy consumption characteristics

Apparatuses comprising data processing circuitry and a wakeup interrupt controller and methods of operating the apparatuses are disclosed. Prior to the processing circuitry entering a low power state, indications of pending interrupts are transferred to the wakeup interrupt controller. Further indications of interrupts received whilst the processing circuitry is in the low power state may be accumulated in the wakeup interrupt controller. When the wakeup interrupt controller receives a wakeup signal, the indications of pending interrupts are transferred to the processing circuitry and the processing circuitry exits the low power state.

Wakeup interrupt controller

A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

Apparatus and branch prediction circuitry having first and second branch prediction schemes, and method

Apparatus for processing data is provided with fetch circuitry for fetching program instructions for execution from one or more active threads of instructions having respective program counter values. Pipeline circuitry has a first operating mode and a second operating mode. Mode switching circuitry switches the pipeline circuitry, between the first operating mode and the second operating mode in dependence upon a number of active threads of program instructions having program instructions available to be executed. The first operating mode has a lower average energy consumption per instruction executed than the second operating mode and the second operating mode has a higher average rate of instruction execution for a single thread than the first operating mode. The first operating mode may utilise a barrel processing pipeline to perform interleaved multiple thread processing. The second operating mode may utilise an out-of-order processing pipeline for performing out-of-order processing.

Mode switching in dependence upon a number of active threads

An apparatus comprises prediction circuitry () for determining, based on current prediction policy information (), a predicted behavior to be used for processing instructions. The current prediction policy information is updated based on an outcome of processing of instructions. A storage structure () stores at least one entry identifying previous prediction policy information () for a corresponding block of instructions. In response to an instruction from a block having a corresponding entry in the storage structure () which identifies the previous prediction policy information (), the current prediction policy information () can be reset based on the previous prediction policy informationidentified in the corresponding entry of the storage structure ().

Determining a predicted behaviour for processing of instructions

An apparatus comprises a processing pipeline comprising out-of-order execution circuitry and second execution circuitry. Control circuitry monitors at least one reordering metric indicative of an extent to which instructions are executed out of order by the out-of-order execution circuitry, and controls whether instructions are executed using the out-of-order execution circuitry or the second execution circuitry based on the reordering metric. A speculation metric indicative of a fraction of executed instructions that are flushed due to a mis-speculation can also be used to determine whether to execute instructions on first or second execution circuitry having different performance or energy consumption characteristics.

Controlling execution of instructions for a processing pipeline having first out-of order execution circuitry and second execution circuitry

A target apparatusfor debug includes a processing pipelinefor executing a sequence of program instructions. A debug interfacereceives debug command signals corresponding directly or indirectly to debug program instructions to be executed. An instruction bufferstores both the debug program instructions and non-debug program instructions. An arbiterselects between both the debug program instructions and the non-debug program instructions stored within the instruction buffer to form the sequence of program instructions to be executed by the processing pipeline. A complex coherent memory systemis shared by the debug program instructions and the non-debug program instructions such that they obtain the same coherent view of memory.

Executing debug program instructions on a target apparatus processing pipeline

A data processing apparatus includes a cache memory supporting parallel data loads involving both a first address and a second address. The first address is compared with TAG values stored within a first value store and the second address is compared in parallel with TAG values stored within a second value store. The second value store contains a proper subset of the data value stored within the first value store.

Parallel lookup in first and second value stores

A data processing apparatus includes error detection and correction circuitry with an associated hard-error memory buffer. When a correctable hard-error is detected associated with a memory access to a memory, if the hard-error memory buffer is already full, then this correctable hard-error is escalated to be handled as an uncorrectable hard-error. The escalated uncorrectable hard-error is then handled by uncorrectable error handling circuitry (fatal error circuitry) which may trigger an abort of corresponding processing operations by a processor core and force the relinquishing of resources within other circuit elements such as a store buffer.

Malfunction escalation

An integrated circuit incorporates prefetch circuitry for prefetching program instructions from a memory. The prefetch circuitry includes a branch target address cache. The branch target address cache stores data indicative of branch target addresses of previously encountered branch instructions fetched from the memory. For each previously encountered branch instructions, the branch target address cache stores a tag value indicative of a fetch address of that previously encountered branch instruction. The tag values stored are generated by tag value generating circuitry which performs a hashing function upon a portion of the fetch address such that the tag value has a bit length less than the bit length of the portion of the fetch address concerned.

Branch target address cache using hashed fetch addresses

A multithreading processorinterleaves program instructions from different program threads to perform fine grained multithreading. Thread performance monitoring circuitrymonitors performance parameters of individual program threads to generate performance values. Issue control circuitryreads these performance values to determine which program thread is next selected to be active when a thread switch event occurs. The performance parameters measured may include the proportion of cycles in which a program thread is able to provide a program instruction for execution by the execution circuitrywithin the processor

Thread selection for multithreaded processing

A data processing and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from a memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in the cache for access by the processing circuitry. If a pre-decoded instruction crosses a cache line boundary, then checking circuitry in respect of selected types of pre-decoded instruction checks for consistency between the first portion of the pre-decoded instruction stored within a first cache line and a contiguous second portion of the pre-decoded instruction stored within a second cache line. If this consistency check is passed such that the two portions are self-consistent, then the pre-decoded instruction can be further decoded and issued. If the consistency check is failed, or the pre-decoded instruction is not of a type for which consistency checking is supported, then re-generation of the pre-decoded instruction is triggered.

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Kettering, United Kingdom

Allan John Skillman