International Business Machines Corporation

Allan Harvey Dansky

Howard Harold Smith

Peter J Camporese

Wiren Dale Becker

Alina Deutsch

Dale E Hoffman

Kwok Fai Eng

Adrian Zuckerman

Bhupindra Singh

Phillip John Restle

Gerard Vincent Kopcsay

Steven John Zier

Michael Alexander Bowen

Fadi Y Busaba

Anthony Gus Aipperspach

Helmut Schettler

Nghia Van Phan

Jack A Dorler

Pierre B Mollier

Gerard Boudon

Dennis C Banker

Walter S Klara

Allan L Mullgrav, Jr

Dennis C Reedy

Ieng Ong

Frank M Masci

John P Norsworthy

Biagio Pluchino

Chris J Rebeor

Kenny K Shin

John F McCabe

Martine M Savalle

A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

Method for evaluating decoupling capacitor placement for VLSI chips

Deterministic evaluation of coupling noise voltage is a function of many physical and electrical parameters such as wiring level, widths, spacing, net topologies, drv impedance and slew rates. This evaluation requires electrical modeling and subsequent circuit simulation to assess the sensitivities of these parameters. These sensitivities can be categorized as coupling guidelines that can be directly linked through extracted physical design data. This invention discloses the development and implementation of a technique for using a coupling guideline table early in the design of an integrated circuit when all the parameters generally required for coupling noise voltage calculations are not available. The steps include: creating a flat wire routing map of the integrated circuit, identifying the coupled wire segments on the integrated circuit, tracking wire interconnection patterns on the integrated circuit, deriving electrical parameters for the coupled wire segments, and generating a coupling guideline table with parameters for a plurality of electrical parameters. The parameters in the coupling guideline table are applied to the derived electrical parameters and a report is generated that lists the derived electrical parameters that fail to comply with the parameters in the coupling guideline table.

Method for performing coupling analysis

A routing program length method for positioning unit pins in a hierarchically designed VLSI chip first identifies unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a &ldquo;flat&rdquo; file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the Incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units. The other pin log is the same, except it does not include the unit pins and the incremental net length associated with the unit pins. A commercially available program, for example, a Minimum Spanning Tree (MST) program or a Steiner Minimal Tree program is run against every net; once against the nets in the pin log list that includes the pins assigned by the designers of the units, and once against the nets in the pin log list that does not include assigned unit pins. The output of interest of the MST (or similar program) run against the net files with and without pin assignments is a text file containing the net names, number of pins per net with and without unit pins and the difference between the net lengths with and without unit pin assignments. If the difference exceeds a threshold value a router program is run in isolation against each net without unit pins. Pins are placed where the wiring route for the net crosses each unit boundary.

Routing program method for positioning unit pins in a hierarchically designed VLSI chip

A method for reducing the computation time and improving the productivity in designing high-performance microprocessor chips that have no failures&mdash;due to crosstalk noise. The technique allows a very fast calculation of tables of frequency-dependent circuit parameters needed for accurate crosstalk prediction on lossy on-chip interconnections. These tables of parameters are the basis for CAD tools that perform crosstalk checking on >10K critical nets on typical microprocessor chips. A fast table generation allows for rapid incorporation of design or processing changes and transition to more advanced technologies.

Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation

A method for identifying and positioning sub-optimally positioned unit pins in a hierarchically designed VSLI chip without modifying unit placement, comprising: generating a flat data file, generating a first pin log using the flat data file including data for unit pins and for macro pins of a net, generating a second pin log using the flat data file including data for macro pins of the net, determining a minimal net length using the first pin log and determining a minimum net length using the second pin log, calculating the difference between the minimal net length determined using the first ping log and the minimal net length determmed using the second pin log, identifying sub-optimally positioned unit pins by comparing the calculated difference to a threshold, and repositioning the identified sub-optimally positioned unit pins.

Minimal length method for positioning unit pins in a hierarchically designed VLSI chip

A method for identifying unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a &ldquo;flat&rdquo; file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units. The other pin log is the same, except it does not include the unit pins and the incremental net length associated with the unit pins. A commercially available program, for example, a Minimum Spanning Tree (MST) program or a Steiner Minimal Tree program is run against every net; once against the nets in the pin log list that includes the pins assigned by the designers of the units, and once against the nets in the pin log list that does not include assigned unit pins. The output of interest of the MST (or similar program) run against the net files with and without pin assignments is a text file containing the net names, number of pins per net with and without unit pins and the difference between the net lengths with and without unit pin assignments. If the difference exceeds a threshold value, that net is identified so that the unit pins can be reassigned by the unit designer or designers.

Method to identify unit pins that are not optimally positioned in a hierarchically designed VLSI chip

A method and system for reducing the computation complexity and improving accuracy of delay and crosstalk calculation in transmission-lines with frequency-dependent losses. An analysis tool based on restricted coupled-line topologies, simple two-dimensional to three-dimensional RLC matrix conversion, and use of prestored synthesized circuits that accurately capture frequency-dependent loss effects. The CAD tool can handle frequency-dependent resistive and inductive effects for coupled-interconnections on large microprocessor chips with >10K of critical nets. This is done in an interactive manner during the design cycle and allows first path fast product design.

System and method for reducing calculation complexity of lossy, frequency-dependent transmission-line computation

A program method for noise calculation and modeling caculates crosstalk voltage for a planned chip design, by first running routing and crosstalk routines for creating crosstalk rules for the planned design of a chip and loading crosstalk rules after routing is completed, and calculating the noise voltage of the planned design based on the exact topologies/paths of the victim and perpetrator nets of the planned design by path tracing and outputing a program file which contains the calculated noise voltage and a complete tabulation of the key physical and electrical parameters of the victim and perpetrator nets of the planned design, and then modeling using a network analysis program to selected nets of the design which exceed allowed noise limitations and obtaining the planned design net's network topology as an output while using the program file containing noise voltage calculation results as an input to the net's topology circuit simulation modeling program and outputting a nodal voltages vs. time data at each receiver location on a victim net as well as key nodes on any perpetrator nets of said planned design.

Calculating crosstalk voltage from IC craftsman routing data

A process and hold system includes a bipolar logic section which is clocked on and off by a first field effect transistor and a bipolar latch section which is clocked on and off by a second field effect transistor. Emitter coupled logic is used in both the logic and latch sections in order to obtain high speed operation. Each of the field effect transistors is used as an on-off switches which has low impedance between the drain and source thereof when enabled and conducting. Outputs of the logic section are coupled to inputs of the latch section. Complementary clock signals are used to control the first and second field effect transistors so that one of the logic and latch section is enabled at a time. The logic section uses a two level emitter coupled tree configuration in order to increase logic capability. The use of the field effect transistors facilitates the use of a power supply having a voltage level of +3.6 volts. This is contrasted with the typical +5 volt supply used with conventional emitter coupled tree configurations. Accordingly, high speed at reduced power dissipation is achieved using the inventive process and hold system.

High-speed bipolar-field effect transistor (BI-FET) circuit

Multi-emitter BICMOS logic circuit family with superior performance

A push-pull driver circuit operative with two input logic signals of opposite sense has a first bipolar transistor with a base terminal connected to a first input signal, and an emitter terminal connected to a second bipolar transistor which takes the place of the emitter resistor in the usual construction of an emitter follower circuit. During an activation of the first transistor to pass current, this being the pull-up stage, the second transistor is in a quiescent state to develop a voltage drop provided by current flow from the first transistor. A current mirror maintains a small quiescent current in the second transistor so that it can be activated rapidly upon occurrence of the pull-down transition. During a deactivation of the first transistor to terminate current flow in the first transistor, the voltage drop across the second transistor decreases, this being the pull-down stage. The voltage drop across the second transistor serves as an output signal of the driver circuit. During the pull down stage, the second transistor is activated momentarily via the capacitance of a back-biased transistor to pass current for rapid reduction of the voltage drop across the second transistor, this being in response to the second input signal. To avoid placing the second transistor in a state of saturation, a bypass transistor is connected across the base-collector terminal of the second transistor in the reverse direction of current flow in the second transistor to prevent the development of excessive base drive to the second transistor.

Low power push-pull driver

A receiver and level converter circuit is disclosed which may be used, for example, in converting low-level logic or other signals to high-level signals. In one embodiment, the circuit includes a differential amplifier having two feedback loops to provide an output signal having hysteresis, for increased gain, better noise margin and compensation. Each feedback loop includes a nonlinear difference network. In a preferred embodiment, the circuit is implemented in BICMOS technology, uses out-of-phase FETs as pull-down devices, and may be used to convert ECL-level signals to CMOS or BICMOS-level signals.

Receiver and level converter circuit with dual feedback

A BIFET logic circuit for quickly switching an output line from a high level to a reference level. The BICMOS circuit comprises a push-pull circuit including a first bipolar transistor for driving current into an output line, and a second bipolar transistor for sinking current from the output line; a CFET logic circuit for performing a logic function and including at least one N type FET for providing current to the base of the second bipolar transistor when a set of input lines to the CFET circuit has a first set of predetermined values; and a resistive means for connecting one of the source or drain of the at least one NFET to a power supply to provide a source of base current to the second bipolar transistor, even when the output line drops in voltage. This circuit is especially advantageous for driving low threshold CFET circuits. In a preferred embodiment, the circuit further includes a device for preventing a voltage differential of more than a predetermined amount between the base and emitter of the first bipolar transistor, to thereby ensure proper push-pull operation of the bipolar transistors.

Growing community of inventors

Poughkeepsie, NY, United States of America

Allan Harvey Dansky