Intel Corporation

Google Inc.

Hewlett-packard Development Company, L.p.

Allan Douglas Knies

Joshua B Fryman

Jason Rupert Redgrave

Manu Gulati

Albert Meixner

Dale Calvin Morris

David Pardo Keppel

Benjamin K Dodge

Keith Robert Pflederer

Vinod Chamarty

Xiaoyu Ma

Hongil Yoon

Rahul Jagdish Thakur

Weiping Liao

Naveen Kumar

Naveen Neelakantam

Dean A Mulla

Shantanu R Gupta

Achmed Rumi Zahir

Salman Abdul Baset

Fernando Latorre

Shinye Shiu

Vyacheslav Vladimirovich Malyugin

Kevin Roland Fall

Ethan Schuchman

Polychronis Xekalakis

Franck Sala

Patrick P Lai

Sylvia Ratnasamy

Jaroslaw Topp

John H Kelm

Denis M Khartikov

Demos Pavlou

Gianluca Iannaccone

Amy L O'Donnell

Chih-Chung Chang

Varun Mohandru

Lutz Naethke

James M Hull

Li-Gao Zei

Santhosh Rao

Kevin W Rudd

Dong Hyuk Woo

Gregor Stellpflug

Rami May

Maziar H Manesh

Masha Lipshits

Lihu Rappaport

Katerina Argyraki

Byung-Gon Chun

Norbert Egi

Mihai Dobrescu

Donald C Soltis

Mirem Hyuseinova Seidahmedova

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.

Way partitioning for a system-level cache

Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.

Apparatus and method for efficiently implementing a processor pipeline

Provided are methods, systems, and apparatus for managing and controlling memory caches, in particular, system level caches outside of those closest to the CPU. The processes and representative hardware structures that implement the processes are designed to allow for detailed control over the behavior of such system level caches. Caching policies are developed based on policy identifiers, where a policy identifier corresponds to a collection of parameters that control the behavior of a set of cache management structures. For a given cache, one policy identifier is stored in each line of the cache.

Memory system architecture

A collective communication apparatus and method for parallel computing systems. For example, one embodiment of an apparatus comprises a plurality of processor elements (PEs); collective interconnect logic to dynamically form a virtual collective interconnect (VCI) between the PEs at runtime without global communication among all of the PEs, the VCI defining a logical topology between the PEs in which each PE is directly communicatively coupled to a only a subset of the remaining PEs; and execution logic to execute collective operations across the PEs, wherein one or more of the PEs receive first results from a first portion of the subset of the remaining PEs, perform a portion of the collective operations, and provide second results to a second portion of the subset of the remaining PEs.

Collective communications apparatus and method for parallel systems

Methods and apparatus to provide failure detection are disclosed herein. An example method to synchronize data operations between multiple workload units in a computing device to facilitate failure detection includes identifying a number of first data operations to write data from a computing node in a first workload unit to locations that are not in a local cache of the computing node and are not in a memory of the first workload unit, the first data operations corresponding to a set of computing instructions that are assigned to the first workload unit and, when a flag in the first workload unit has been set to a first value, synchronizing the first data operations with second data operations by a second workload unit.

Methods and apparatus to provide failure detection

A method, system, and computer program product for identifying loop information corresponding to a plurality of loop instructions. The loop instructions are stored into a queue. The loop instructions are replayed from the queue for execution. Loop iteration is counted based on the identified loop information. A determination is made of whether the last iteration of the loop is done. If the last iteration is not done, then embodiments continue replaying the loop instructions, until the last iteration is done.

System of improved loop detection and execution

Responsive to execution of a computer instruction in a current translation window, state indicators associated with a cache line accessed for the execution may be modified. The state indicators may include: a first indicator to indicate whether the computer instruction is a load instruction moved from a subsequent translation window into the current translation window, a second indicator to indicate whether the cache line is modified in a cache responsive to the execution of the computer instruction, a third indicator to indicate whether the cache line is speculatively modified in the cache responsive to the execution of the computer instruction, a fourth indicator to indicate whether the cache line is speculatively loaded by the computer instruction, a fifth indicator to indicate whether a core executing the computer instruction exclusively owns the cache line, and a sixth indicator to indicate whether the cache line is invalid.

Cache coherency and processor consistency

Generally, this disclosure describes a scalable cluster router that includes a plurality of server-class computers interconnected together to form a router. Each server may be configured to independently schedule switching of packets to reduce the switch speed requirements on a per server basis. Each server may include a scheduler that independently load balances packet flows across servers of the cluster. Router capacity may be incrementally scaled by adding more servers, and router capacity may be increased by load balancing techniques within individual servers.

Scalable cluster router

Methods and apparatus to provide failure detection are disclosed herein. An example method includes executing, via a plurality of computing nodes, first fenced computing operations; storing a count of issued data operations resulting from the first fenced computing operations; and determining whether a failure condition exists in the plurality of computing nodes by comparing the count of issued data operations to the count of performed data operations resulting from the first fenced computing operations.

Atomic sixteen-byte memory accesses are provided in a 64-bit system in which eight of the bytes are stored in a 64-bit general-purpose register and eight of the bytes are stored in a 64-bit special-purpose register. A 16-byte load instruction transfers the low eight bytes to an explicitly specified general-purpose register, while the high eight bytes are transferred to the special-purpose register. Likewise, a 16-byte store instruction transfers data from a general-purpose register and the special-purpose register. Also provided is an 8-byte compare conditioning a 16-byte exchange semaphore instruction that can be used to accelerate algorithms that use multiple processors to simultaneously read and update large databases.

Superword memory-access instructions for data processor

A processor comprising a feature indicator associated with at least one of a first sequence of one or more instructions, a first register, a second register, and an execution core is provided. The execution core is configured to execute a second instruction to cause the first register to be set to a first value using the feature indicator and to cause the second register to be set to a second value using the feature indicator. The execution core is configured to execute the first sequence of one or more instructions to cause a function to be performed in response to the first value in the first register indicating a true condition, and the execution core is configured to execute a second sequence of one or more instructions to cause the function to be performed in response to the second value in the second register indicating the true condition.

System and method for adding an instruction to an instruction set architecture

Growing community of inventors

Burlingame, CA, United States of America

Allan Douglas Knies