Broadcom Corporation

Silicon Graphics, Incorporated

Allan Christie

Daniel Talayco

Mohan V Kalkunte

Shekhar Ambe

Uri Elzur

Shiri Kadambi

Sandeep Kumar Relan

Martin Lund

Brian R Baird

David Edward McCracken

James A Stuart Fiske

A method for establishing a virtual channel between network devices is disclosed. In the case of a local network device establishing a virtual channel with a remote network device, a virtual channel request message is sent from the local network device to the remote network device. A virtual channel acknowledgement message and a remote capability list are received and a virtual channel resume message and a local capability list are sent. The virtual channel is then enabled. In the case of a remote network device establishing a virtual channel with a local network device, a virtual channel request message is received from a local network device by a remote network device. A virtual channel acknowledgement message and a remote capability list are sent and a virtual channel resume message and a local capability list are received. The virtual channel is then enabled.

Multiple logical channels for use in network devices

A method, system and apparatus for decoupling devices in a network for use by a system-wide application. The invention includes accumulating configuration information for the network, wherein the network includes a plurality of units, and each of the units includes a processor and at least one switch device. The invention further includes analyzing the configuration information and determining a logical configuration for the network based on the analyzed configuration information. The invention further includes virtually attaching a remote switch device to the network.

Virtual system configuration

Multiple virtual channels for use in network devices

A memory protection system for shared memory in a multiprocessor computer is provided that comprises a multiprocessor computer ( ) having a plurality of processor regions and a plurality of memory pages ( ). Each processor region includes one or more processors ( ). Each processor ( ) includes a cache ( ), and each memory page ( ) includes one or more cache lines ( ) for coupling to the cache ( ) of processors ( ) within the plurality of processor regions using the memory page ( ). Each memory page ( ) includes a set of protection bits ( ) associated with each processor region in the plurality of processor regions. The set of protection bits ( ) includes an acquire protection bit ( ) for each processor region in the plurality of processor regions. The acquire protection bit ( ) determines whether the associated processor is enabled to perform acquire operations on the memory page ( ). The set of protection bits ( ) also includes a release protection bit ( ) for each processor region in the plurality of processor regions. The release protection ( ) determines whether the associated processor is enabled to perform release operations on the memory page ( ).

System and method for shared memory protection in a multiprocessor computer

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Fremont, CA, United States of America

Allan Christie