Nxp Usa, Inc.

Freescale Semiconductor,inc.

Alistair Robertson

Mark Maiolani

Alan Devine

Carl Culshaw

Robert Freddie Moran

William C Moyer

James Andrew Collier Scobie

Jeffrey William Scott

Joseph Charles Circello

Ray Charles Marshall

Garima Sharda

Manfred P Thanner

Akshay Kumar Pathak

Andrew Edward Birnie

Alison Young

William Ernest Edwards

Mike Robert Garrard

Derek Beattie

Jimmy Gumulja

Michael Robert Garrard

Rolf Dieter Schlagenhaft

Philippe Mounier

Jeffrey Thomas Loeliger

Nancy H Amedeo

Michael Johnston

Andrey Kovalev

Alan R Duncan

Andrei Kovalev

Gerard William Humphries

Murray Douglas Stewart

Geoff Emerson

A processor includes an instruction pipeline. The pipeline can be operated alternatively in a multi-thread mode and in a single-thread mode. In the multi-thread mode, the instruction pipeline processes multiple threads in an interleaved or simultaneous manner. In the single-thread mode, the pipeline processes a single thread. The instruction pipeline comprises multiple functional units, each of which is reserved for one thread among the multiple threads when the pipeline is in the multi-thread mode and reserved for one context layer among multiple context layers when the instruction pipeline is in the single-thread mode.

Integrated circuit processor and method of operating the integrated circuit processor in different modes of differing thread counts

A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in parallel. In response to a task identifier being received that is indicative of a task requiring an improved level of determinism, the dual-issue capability of at least one of the first thread or the second thread is temporarily disabled.

Providing task-triggered deterministic operational mode for simultaneous multi-threaded superscalar processor

A system on chip, comprising a processing unit for executing processes, a memory unit, and a memory control unit connected between the processing unit and the memory unit, is described. The memory control unit allocates a memory region to a process. The memory control unit comprises a process activity counter which counts a duration of the process or transactions by the process to or from the memory region and which maintains a process activity count representing the counted duration of the process or the counted transactions to or from the memory region. The memory control unit disables the memory region in response to the process activity count exceeding a maximum process activity count. Notably, it blocks the memory region against further transactions by the process and against transactions by any other processes. A method of operating a system on chip is also described.

System on chip and method of executing a process in a system on chip

A method of detecting overcurrent events within at least one electronic device, and an overcurrent detection module therefor. The method comprises receiving at least one current requirement indication from at least one electronic device, determining at least one overcurrent value based at least partly on the received at least one current requirement indication, receiving at least one indication of at least one input current flow for the at least one electronic device, and determining that an overcurrent event is occurring if the indicated at least one input current flow for the at least one electronic device exceeds the determined at least one overcurrent value.

Method and apparatus for detecting and managing overcurrent events

A processor system includes at least two processor cores and an interrupt controller including interrupt priority registers configured for registering interrupt priorities of the respective processor cores. The processor system further includes at least two task timers associated with respective processor cores. Each task timer includes a counter configured for producing a counter value, a timeout value register configured for storing a timeout value and a tidemark value register configured for storing a tidemark value smaller than the timeout value. Each task timer is configured for producing a timeout signal when the counter value equals the timeout value and for producing a tidemark signal when the counter value equals the tidemark value. The interrupt controller is configured for increasing the interrupt priority of a processor core in response to a tidemark signal and for decreasing the interrupt priority of a processor core in response to a timeout signal.

Multiple processor core interrupt priority levels

An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. The technique may include providing a base address and a transfer trigger to initiate the transferring of the peripheral data. The technique may include executing a peripheral interrupt service routine after executing the interrupt service routine prologue. The technique may include executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including resetting an interrupt status flag associated with the interrupt request. Executing the interrupt service routine may include executing instructions using the peripheral data at a rate at least an order of magnitude faster than an access time of the peripheral.

Interrupt-controlled direct memory access peripheral data transfer

A processing system comprising a first processing domain and a second processing domain. Each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core. The processing system further comprises a supervisor component arranged to receive the sets of internal state signals output by the processor cores of the first and second processing domains, compare internal state signals output by the processor core of the first processing domain to corresponding internal state signals output by the processor core of the second processing domain, and upon detection of a mismatch between compared internal state signals to initiate a reset of a thread under the execution of which the detected mismatch of internal state signals occurred.

Method and apparatus for managing mismatches within a multi-threaded lockstep processing system

A method of controlling access by a master to a peripheral includes receiving an interrupt priority level from an interrupt controller associated with the peripheral, comparing the interrupt priority level with respective a pre-established interrupt access level to obtain an interrupt level comparison result, establishing whether an access condition is satisfied in dependence on the interrupt level comparison result, and if the access condition is satisfied, granting access. If the access condition is not satisfied, access is denied. Further, a circuitry is described including a master, a peripheral, and an access control circuitry including an interrupt controller associated with the peripheral. The access control circuitry is arranged to perform a method of controlling access by the master to the peripheral.

Method of and circuitry for controlling access by a master to a peripheral, a method of configuring such circuitry, and associated computer program products

A method of establishing pre-fetch control information from an executable code is described. The method comprises inspecting the executable code to find one or more instructions corresponding to an unconditional change in program flow during an execution of the executable code when the executable code is retrieved from a non-volatile memory comprising a plurality of NVM lines. For each unconditional change of flow instruction, the method comprises establishing a NVM line address of the NVM line containing said unconditional change of flow instruction; establishing a destination address associated with the unconditional change of flow instruction; determining whether the destination address is in an address range corresponding to a NVM-pre-fetch starting from said NVM line address; establishing a pre-fetch flag indicating whether the destination address is in the address range corresponding to a NVM-pre-fetch starting from said NVM line address; and recording the pre-fetch flag in a pre-fetch control information record.

Method of establishing pre-fetch control information from an executable code and an associated NVM controller, a device, a processor system and computer program products

A peripheral integrated circuit (IC) device for providing support to a data processing IC device. The peripheral IC device comprises a fault detection component arranged to detect an occurrence of fault conditions within the data processing IC device. The peripheral IC device further comprises a safe state control component. Upon detection of a fault condition occurring within the data processing IC device by the fault detection component, the safe state control component is arranged to cause at least one I/O cell of the data processing IC device to be configured into at least one scan-chain, and cause at least one predefined control signal to be scanned into the at least one scan-chain to configure the at least one I/O cell into a state corresponding to the predefined control signal.

Method and apparatus for configuring I/O cells of a signal processing IC device into a safe state

A data path configuration component for configuring at least one data path setting within a signal processing device is described. The data path configuration component is arranged to receive an indication of an operating mode of the signal processing device, and dynamically configure the at least one data path setting within the signal processing device based at least partially on the received indication of an operating mode of the signal processing device.

Data path configuration component, signal processing device and method therefor

A method for providing memory protection within a signal processing system comprises receiving a memory access signal comprising at least one instruction memory region (IMR) indication. The IMR indication comprises an indication of a region of memory from which a memory access instruction was fetched, execution of said memory access instruction having resulted in the generation of the received memory access signal. The method further comprises comparing the IMR indication for the received memory access signal to at least one permitted memory region (PMR) indication for a target address of the received memory access signal, and determining whether a memory access being attempted by the memory access signal is permitted based at least partly on the comparison of the IMR indication for the received memory access signal to the PMR indication for the target address of the received memory access signal.

Method and apparatus for providing memory protection

An error response method for a mixed criticality system includes assigning a safety level to an application executed by a processor. Executing the application includes a transaction between the processor and a resource. The safety level is stored at the resource. The safety level and a fault indication are transmitted from the resource to a fault collection and control unit (FCCU). The fault indication is responsive to a fault from the resource. The FCCU responds to the fault indication with an action determined by the safety level.

Safety level specific error response scheme for mixed criticality systems

A signal processing system comprising at least one master device at least one memory element and prefetch module arranged to perform prefetching from at least one memory element upon a memory access request to the at least one memory element from the at least one master device. Upon receiving a memory access request from the at least one master device, the prefetch module is arranged to configure the enabling of prefetching of at least one of instruction information and data information in relation to that memory access request based at least partly on an address to which the memory access request relates.

Signal processing system and integrated circuit comprising a prefetch module and method therefor

High frequency detection of interrupts includes incrementing a count by a first number in response to at least one interrupt. The count is decremented by a second number in response to a clock if the count is greater than zero. An interrupt rate is determined from the count. A fault collection unit (FCU) is updated when the interrupt rate exceeds a threshold.

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Glasgow, United Kingdom

Alistair Robertson