Imagination Technologies Limited

Alistair Goudie

Ian King

Michael John Livesley

Panagiotis Velentzas

Mark Landers

A processor includes a blocking circuit between an upstream section and a downstream section of a hardware pipeline, and control circuitry which triggers the upstream section to process an upstream phase of a first task, with the blocking circuit in an open state whereby first data from the processing of the upstream phase of the first task passes through from the upstream section to be processed in a downstream phase of the first task. In response to detecting that the upstream section has finished processing the upstream phase of the first task, the control circuitry triggers the upstream section to start processing a second task while the downstream section is still processing the downstream phase of the first task, and switches the blocking circuit to a closed state blocking second data from the processing of the upstream phase of the second task passing to the downstream section.

Processor with hardware pipeline

A processor and a method of obtaining data for a processor are provided. The processor comprises at least a first core, a second core, and a distributed cache. The distributed cache comprises a first cache slice connected to the first core and a second cache slice connected to the second core and to the first cache slice. The first cache slice is configured to receive a memory access request from the first core and forward the memory access request to the second cache slice.

Distributed system level cache

A graphics processor including geometry and fragment processing logic, and a memory manager arranged to allocate and deallocate memory for use to hold tile data. The memory manager tracks which memory regions are allocated to hold tile data of which subdivisions (e.g. macrotiles) of the render area. Once the fragment processing logic has finished processing the tile data of a subdivision, it sends an identifier of that subdivision to the memory manager for deallocation. The processor further comprises a blocking circuit enabling the fragment processing logic to start processing tile data of a second task while the memory manager is still deallocating some of the memory regions allocated to the subdivisions of a first task; by preventing identifiers of subdivisions of the second task being passed to the memory manager until it has completed deallocating the memory regions allocated to the first task.

Graphics processor

A method of processing rays in a ray tracing system, the method comprising: allocating a block of memory for a task on a per-task basis; processing rays in the task causing at least one child ray to be emitted; writing intermediate data for the task to said block of memory; suspending processing of the task; and when the task is ready to resume, reading intermediate data for the task from the block of memory, and resuming the processing of the task.

Memory allocation in a ray tracing system

Logic includes a task builder for building tasks comprising data items, a task scheduler for scheduling tasks for processing by a parallel processor, a data store arranged to map content of each data item to an item ID, and a linked-list RAM comprising an entry for each item ID. For each new data item, the task builder creates a new task by starting a new linked list, or adds the data item to an existing linked list. In each linked list, the entry for each data item records a pointer to a next item ID in the list. The task builder indicates when any of the tasks is ready for scheduling. The task scheduler identifies a ready task based on the indication from the task builder, and in response follows the pointers in the respective linked list in order to schedule the data items of the task for processing.

Building and scheduling tasks for parallel processing

A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.

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Hertfordshire, United Kingdom

Alistair Goudie