Arm Limited

International Computers Limited

Alistair Crone Bruce

Andrew David Tune

Antony John Harris

Bruce James Mathewson

Sean James Salisbury

Robin Hotchkiss

Simon Crossley

Nigel Rowland Crocker

Muhammed Mutaher Hashmi

Peter Andrew Riocreux

Timothy Charles Mace

Andrew Mark Nightingale

Louisa Jayne McElwee

Data processing apparatus comprises one or more transaction issuing devices configured to issue data processing transactions to be handled by a downstream device and to receive a completion acknowledgement in respect of each completed transaction; each transaction issuing device having associated transaction regulator circuitry configured to allow that transaction issuing device to issue transactions subject to a limit on a maximum number of outstanding transactions, an outstanding transaction being a transaction which has been issued but for which a completion acknowledgement has not yet been received; in which the downstream device is configured to issue an indication to a transaction issuing device, to authorize a change by the transaction regulator circuitry of the limit applicable to outstanding transactions by that transaction issuing device.

Data processing

An arbiter is configured to select one of several contending data packets transmitted from an initiator, the data packets comprising an identifier identifying the initiator and data. The arbiter comprises: a history buffer for storing the identifiers identifying the initiators of a plurality of recently selected data packets; and selection circuitry configured to select one of the contending data packets in dependence upon the initiators of the contending data packets and the initiators identified in the history buffer, such that a probability of a data packet being selected increases with the number of data packets selected since a data packet from the same initiator was selected.

Selecting between contending data packets to limit latency differences between sources

A data processing apparatus is provided with a master device and a slave device which communicate via communication circuitry. The slave device is associated with a predetermined number of permission tokens that is equal to a maximum number of currently pending messages that can be accepted for processing from the communication circuitry by that slave device. The slave device transmits these permission tokens to the master device. The master device takes exclusive temporary possession of the permission tokens that it receives such that the permission tokens are then no longer available to any other master device. A master device initiates a message to a slave device when the master device has exclusive temporary possession of a permission token for that slave device. When the master device has initiated its message, then it relinquishes the exclusive temporary possession of the permission token such that it is then available for other devices.

Receiver based communication permission token allocation

Buffer circuitryis provided with shared buffer circuitrywhich stores, in order of reception time, data transaction requests received from one or more data transaction sources. The buffer circuitryoperates in either a bypass mode or a non-bypass mode. When operating in the bypass mode, any low latency data transaction requests stored within the shared buffer circuitry are selected in order for output in preference to data transaction requests that are not low latency data transaction requests. In the non-bypass mode, transactions (whether or not they are low latency transactions) are output from the shared buffer circuitryin accordance with the order in which they are received into the shared buffer circuitry. The switch between the bypass mode and the non-bypass mode is made in dependence upon comparison of a detected rate of output of low latency data transaction requests compared to a threshold value. If the rate exceeds the threshold value, then the switch is made to the non-bypass mode so that data transaction requests which are not low latency data transaction requests are permitted a fair share of the output bandwidth.

Low latency bypass buffer

An apparatus and method are provided for performing verification tests for a design of a data processing system. The apparatus comprises a system under verification representing at least part of the design of the data processing system, and a transactor for connecting to an interface of the system under verification, and for generating signals for input to the system under verification via the interface during performance of the verification tests. Profile storage stores a profile providing a statistical representation of desired traffic flow at the interface, the statistical representation providing statistical information for a plurality of traffic attributes and also identifying at least one dependency between such traffic attributes. The transactor then references the profile in order to determine the signals to be generated, such that the signals generated take account of the specified dependencies identified in the profile. Such a mechanism enables the transactor to more realistically replicate the traffic flow that will be observed in the real system. Another aspect to the present invention provides a mechanism for generating such profiles.

Use of statistical representations of traffic flow in a data processing system

An integrated circuit includes a signal source and a signal destination linked by a signal path. Error correction codes (e.g. Hamming codes) are applied to the signals to be transmitted. Errors detected in the signal transmission are used to control an operating parameter of the signal path, such as signal voltage level, body bias voltage, clock frequency and/or temperature. The control applied is closed-loop feedback control seeking to maintain a finite non-zero predetermined error rate. The technique can also be used between a memory accessing integrated circuit and a separate memory integrated circuit. Furthermore, the technique can be used to provide fixed, but differing operating parameters for signal lines within a signal path. Control signals which may be timing critical are passed with appropriate operating parameters, such as a high signal voltage level, where as other signals, such as address and data signals, are passed with a different appropriate operating parameter, such as a low signal voltage level.

Operating parameter control for integrated circuit signal paths

A data processing apparatus and method for measuring a value of a predetermined property of transactions are provided. The data processing apparatus has initiator circuitry for initiating transactions, recipient circuitry for handling each transaction initiator by the initiator circuitry, and a communication path interconnecting the initiator circuitry and the recipient circuitry via which the transactions are propagated between the initiator circuitry and the recipient circuitry. Measurement circuitry is coupled to the communication path for measuring a value of a predetermined property of the transactions, such as the latency of those transactions. The measurement circuitry has active transaction count circuitry for maintaining an indication of the number of transactions in progress, and accumulator circuitry for maintaining an accumulator value which is increased dependent on the number of transactions in progress. Further, a value register is provided for maintaining an estimate of the value of the predetermined property. Each time a transaction in progress reaches a predetermined point, for example a transaction end point, the accumulator value is decreased dependent on the estimate currently stored in the value register, and further the estimate stored in the value register is updated dependent on the accumulator value. Via this feedback mechanism, the estimate stored in the value register quickly settles to the actual value of the predetermined property being measured, and accordingly such measurement circuitry provides a simple, low cost and flexible mechanism for measuring the value of a predetermined property of transactions.

Data processing apparatus and method for measuring a value of a predetermined property of transactions

A bus interconnect device is provided comprising a parallel plate waveguide for coupling together a plurality of devices. This provides an efficient and flexible approach for providing interconnect functionality within a data processing apparatus.

Bus interconnect device and a data processing apparatus including such a bus interconnect device

A data processing apparatus, bus logic and method are provided for controlling power consumption within a data processing apparatus. The data processing apparatus has a plurality of logic elements, at least one of the logic elements being an initiator logic element for initiating transfers, and at least one of the logic elements being a recipient logic element for receiving transfers. A communication path is provided between an initiator logic element and a recipient logic element to enable payload data the subject of a transfer to be passed from the initiator logic element to the recipient logic element. The communication path has at least one buffer circuit provided therein for propagating at least the payload data along the communication path. Further, a power control circuit is associated with the at least one buffer circuit, which is responsive to a control signal indicating whether the payload data on the communication path is valid. If the control signal indicates that the payload data is not valid, the power control circuit causes the associated at least one buffer circuit to enter a power saving state. The control signal is derived from at least one pre-existing signal associated with the transfer. This has been found to provide a particularly efficient and flexible technique for reducing leakage current in buffer circuits within the data processing apparatus.

Controlling power consumption in a data processing apparatus

A memory controller includes a write data cache, a read data cache and coherency circuitry. The coherency circuitry manages coherency of data between the write data cache, the read data cache and data stored within a main memory when servicing read requests and write requests received by the memory controller. Write complete signals are issued back to a write requesting circuit as soon as a write request has had its write data stored within the write data cache.

Memory controller with write data cache and read data cache

An adaptor circuitfor peripheral devicesis provided with a direct memory access manager. This local direct memory access manageris able to autonomously manage data transfers on behalf of its associated peripheral device. A computer program tools used to generate signal interconnectsis used to additionally specify whether a DMA capability is to be provided for a peripheral device, whereupon an adaptor circuitincluding a DMA managercan be included within the signal interconnect. A DMA command signal is added to the interconnect signals being passed around the signal interconnectand enables DMA command/configuration data to be distributed using the existing signal distribution infrastructure and addressed to the associated peripheral deviceof the target local DMA controller. Existing software drivers can issue control information to a main central DMA controller, which then passes this information on to a DMA Capable adaptor circuitto manage the transfer concerned. Thus the present technique can be used without requiring software drivers to be rewritten.

Distributed direct memory access provision within a data processing system

A data processing apparatus and method are providing for arbitrating access to a shared resource. The data processing apparatus has a plurality of logic elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests by one or more of the logic elements for access to the shared resource to perform a priority determination operation to select one of the requests as a winning request. The arbitration circuitry applies an arbitration policy to associate priorities with each logic element, the arbitration policy comprising multiple priority groups, each priority group having a different priority and containing at least one of the logic elements. Within each priority group, the arbitration circuitry applies a priority ordering operation to attribute relative priorities to the logic elements within that priority group. Responsive to a predetermined event, the arbitration circuitry re-applies the priority ordering operation within at least one priority group prior to a subsequent performance of the priority determination operation. Such an approach has been found to provide a particularly flexible mechanism for performing arbitration, allowing a wide variety of different arbitration schemes to be implemented using the same arbitration hardware.

Data processing apparatus and method for arbitrating access to a shared resource

An interconnect logic and method are provided for controlling transaction reordering by slave logic units coupled to the interconnect logic. The interconnect logic couples master logic units and slave logic units to enable transactions to be performed, each transaction having a transaction identifier associated therewith. ID aliasing logic is associated with at least a subset of slave logic units, with each slave logic unit in that at least a subset being able to issue response transfers for different transactions out of order with respect to the order of receipt by that slave logic unit of the address transfers of those transactions. For at least a subset of the transactions, if the slave logic unit involved in that transaction is associated with the ID aliasing logic, the ID aliasing logic is operable to replace the transaction identifier for that transaction with a predetermined identifier and then to forward the address transfer of the transaction along with that predetermined identifier to the slave logic unit. For any transactions that have their transaction identifier replaced with the predetermined identifier, the slave logic unit will not then perform any reordering since the same identifier, namely the predetermined identifier, is associated with each of those transactions. For any response transfer issue by the slave logic unit with the predetermined identifier, the ID aliasing logic replaces that predetermined identifier with the original transaction identifier removed previously so as to enable the routing of that data transfer via the interconnect logic to the appropriate master logic unit. This provides a very simple and effective mechanism for reducing the occurrence of a deadlock within the interconnect logic.

Interconnect logic for a data processing apparatus

A verification environment is provided that co-verifies a software componentand a hardware component. Within the same environment using a common test controllerboth hardware stimuli and software stimuli may be applied to their respective simulators. The response of both the software and the hardware to the simulation conducted can be monitored to check for proper operation.

Software and hardware simulation

An apparatus for arbitration within a data processing apparatus between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit. The plurality of paths include a shared connection, the data processing apparatus having a plurality of initiator logic elements for initiating transfers and a plurality of recipient logic elements for receiving transfers, for each transfer the corresponding path coupling the initiator logic element responsible for initiating that transfer with the recipient logic element destined to receive that transfer. The apparatus provides arbitration logic with an indication as to whether the ready signal from a storage element has been asserted, and employs the arbitration logic to select, in dependence on predetermined criteria including at least that indication, one of the plurality of transfers for routing via the shared connection.

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Stockport, United Kingdom

Alistair Crone Bruce