Broadcom Corporation

Alireza Zolfaghari

Hooman Darabi

Henrik Tholstrup Jensen

Mohammad Nariman

Ahmad Mirzaei

Ahmadreza Rofougaran

Bojko Frederik Marholev

Chin-Ming Chien

Brima Babatunde Ibrahim

Hea Joung Kim

Kambiz Shoarinejad

Steven Deane Hall

Bojko F Marholev

Paul Anthony Lettieri

Behnam Mohammadi

Koji Kimura

Louie Serrano

According to one disclosed embodiment, an on-chip resistor calibration circuit includes an RC oscillator having a test resistor and a precision capacitor as elements, a counter, and a reference clock. In one embodiment, an RC oscillator generates a waveform having a period dependent upon the resistance of the test resistor and the capacitance of the precision capacitor. In such an embodiment, a counter and a reference clock may be configured to measure the period of the waveform. Using a pre-determined capacitance of the precision capacitor, a resistance of the test resistor may be determined. In another embodiment, an RC oscillator generates first and second waveforms through use of an additional capacitor that can be switched in and out of the RC oscillator circuit. Using a pre-determined capacitance of the precision capacitor, an RC product of the test resistor and the additional capacitor may be determined.

On-chip resistor calibration in semiconductor devices

Various embodiments are disclosed relating to power control techniques for wireless transmitters. In an example embodiment, an apparatus is provided that may include a digital-to-analog converter (DAC) adapted to convert a digital amplitude signal to an analog amplitude signal during a first transmission mode and adapted to convert a digital power level signal to an analog power level signal during a second transmission mode.

Power control techniques for wireless transmitters

A mobile communication device is provided that has a transceiver including a voltage controlled oscillator (VCO) and a calibration circuit for calibrating the VCO. The calibration circuit includes a logic block configured to estimate a calibration value for a tuning of the VCO to a desired frequency, and an asynchronous counter configured to execute a counting sequence to identify a frequency of the VCO after the tuning of the VCO using the calibration value, where the calibration circuit is configured to determine a tuned calibration value for producing the desired frequency from the counting sequence.

Voltage controlled oscillator calibration

System and method for on-chip resistor calibration in semiconductor devices

Various embodiments are disclosed relating to wireless systems, and also relating to transmitter amplifiers, such as, for example, polar transmitter amplifiers with variable output power. According to an example embodiment, a circuit is provided including a plurality of selectable amplifier cells. Each amplifier cell may receive a phase or frequency modulated signal and an amplitude modulated signal. Each amplifier cell may output a signal based upon a combination of the received amplitude modulated signal and the received phase or frequency modulated signal if the amplifier cell is selected. The circuit may provide a variable output current or output power based upon the selection of one or more of the amplifier cells.

Polar transmitter amplifier with variable output power

According to an example embodiment, an apparatus may be provided that is configurable to operate in either a separate power amplifier configuration or a combined power amplifier configuration.

Configurable transmitter

A phase locked loop (PLL) a phase detector, a charge pump, a loop filter, a controlled oscillator, and a feedback divider. The phase detector is coupled to produce a difference signal based on a difference between phase of a reference oscillation and phase of a feedback oscillation. The charge pump is coupled to convert the difference signal into an up-signal or a down signal. The loop filter coupled to filter the up signal or the down signal to produce a control signal. The controlled oscillator is coupled to generate an output oscillation based on the control signal. The feedback divider is coupled to generate the feedback oscillation from the output oscillation based on a divider value. The loop filter includes a first resistor-capacitor circuit and a second resistor-capacitor circuit. The first resistor-capacitor circuit is calibrated using a first calibration technique and the second resistor-capacitor circuit is calibrated using a second calibration technique.

RF transmitter with stable on-chip PLL

An apparatus comprising a plurality of switchable full step mixer unit cells, wherein each switchable full step unit cell is configured to, when the full step transceiver mixer unit cell is turned on, increase the gain experienced by an electronic signal by a full step increment, and wherein the step increment is substantially constant regardless of temperature; and at least one switchable partial step mixer unit cell configured to, when the partial step transceiver mixer unit is turned on, increase the gain experienced by the electronic signal by a predetermined step increment less than that of a full step, and wherein the partial step increment is substantially constant regardless of temperature.

Gain-control methods of transmitter modulators

In an envelope comparison embodiment, a delay calibrator produces a delay signal based on a comparison of a feedback signal and an envelope component of the transmitted signal. A down-converter produces the feedback signal from an outgoing modulated RF signal based on at least one local oscillation. Envelope detectors in the delay calibrator and the envelope signal path are operably coupled to a summing node that produces a delay error signal based on a temporal difference between the two envelopes. One embodiment includes phase detectors to detect and adjust the zero crossings of the feedback signal and the envelope signal path. As the delay mismatch between the envelope signal path and the phase signal path increases, the power spectrum increases in adjacent communication channels. A mask margin measurement technique measures the power level in an adjacent channel and adjusts the envelope path delay accordingly.

Architectural techniques for envelope and phase signal alignment in RF polar transmitters using power amplifier feedback

Aspects of a method and system for processing signals via an integrated low noise amplifier having a configurable input signaling mode are provided. In this regard, one or more circuits comprising an integrated amplifier may be configurable such that, in a first configuration, the one or more circuits are operable to handle a differential input signal, and, in a second mode of operation, the one or more circuits are operable to handle a single-ended input signal. The one or more circuits may output a differential signal when handling a differential input signal and when handling a single-ended input signal. In some instances, whether the one or more circuits are operable to handle a differential input signal or a single-ended input signal may determined by an inductance of a bond wire coupling the integrated amplifier to an integrated circuit package.

Method and system for processing signals via an integrated low noise amplifier having configurable input signaling mode

A radio frequency (RF) transmitter front-end includes a digital to analog conversion module and a power amplifier module. The digital to analog conversion module is coupled to convert amplitude information into analog amplitude adjust signals when a first mode is active and is coupled to convert power level information into analog power level signals when a second mode is active. The power amplifier module is coupled to amplify first phase modulated RF signals in accordance with the analog amplitude adjust signals to produce first outbound RF signals when the first mode is active and is coupled to amplify second phase modulated RF signals in accordance with the analog power level signals to produce second outbound RF signals when the second mode is active.

RF transmitter front-end and applications thereof

Aspects of a method and system for clock synchronization in a GNSS receiver are provided. In this regard, generation of a clock signal in a GNSS receiver may be disabled during a first time interval and enabled during a second time interval, wherein a counter utilized to generate the clock signal may be initialized to a known value during the first time interval via a reset signal synchronized to a reference signal. The reference signal may be generated by a temperature compensated crystal oscillator. Additionally, a counter may be incremented on each active edge of the reference signal that occurs during the first time interval and the value stored in the timer may be utilized to correct time in the GNSS receiver after the first time interval. In this regard, the value stored in the timer may be added to the time at which the first interval began.

Method and system for clock synchronization in a global navigation satellite system (GNSS) receiver

Methods and systems for optimal frequency planning for an integrated communication system with multiple receivers may include adjusting a center frequency of a low IF signal to reduce interference by a second order interference signal. The center frequency may be adjusted to avoid high power portions of the second order interference signal. The interference level corresponding to a center frequency may be determined by, for example, a SNR of the low IF signal, or by determining a BER for the low IF signal. The center frequency of the low IF signal may be dynamically adjusted to keep second order interference level at an acceptable level. Adjusting the center frequency of the low IF signal may also comprise keeping the low IF signal from being blocked by a DC component of the second order interference signal.

Growing community of inventors

Irvine, CA, United States of America

Alireza Zolfaghari