Stmicroelectronics S.r.l.

Politecnico Di Milano

Alireza Tajfar

Marco Zamprogno

A level-shifter includes an input node coupled to a laser driver input receiving a trigger signal, the input node receiving a signal indicating generation of a laser drive-pulse. A p-channel transistor has a source coupled to a supply node, a drain coupled to an output node, and a gate coupled to the input node. An n-channel transistor has a drain coupled to the drain of the p-channel transistor, a source coupled to ground, and a gate coupled to the input node. A first switch couples the input node to the output node. Another p-channel transistor has a source coupled to the supply node, a drain coupled to the output node by a second switch, and a gate coupled to the input node. The first switch closes and second switch opens when the signal is low, and the first switch opens and second switch closes when the signal is high.

Laser driver incorporating clamping circuit with freewheeling diode

A pulsed signal generator generates a pulsed signal having a pulse width intended to be equal to a given fraction of a pulse width of a reference clock. A reference current source outputs current having a reference magnitude, and a comparison current source outputs current having a magnitude that is a function of the reference magnitude and the given fraction. A comparison circuit compares a total current output by one of the reference current source and the comparison current source during pulses of the reference clock to a total current output by the other of the reference current source and the comparison current source during pulses of the pulsed signal equal in number to the pulses of the reference clock in order to determine whether the pulse width of the pulse signal is less than or equal to the given fraction of the pulse width of the reference clock.

Pulse width check circuit for laser diode pulse generator

A monostable circuit includes a delay cell with a reference generator generating a reference current based upon a PVT invariant resistance and a threshold voltage, and a delay block with an output capacitor and an output circuit altering an amount of charge stored on the output capacitor as a function of the reference current, in response to an input signal. An inverter has an input coupled to the output circuit. A logic circuit logically combines output of the inverter and the input signal to generate a monostable trigger pulse. The output circuit includes a current source sourcing the reference current to the output capacitor in response to a first logic state of an input signal, and a current sink sinking current from the output capacitor to discharge the output capacitor, in response to a second logic state of the input signal.

PVT compensated delay cell for a monostable

A circuit includes a capacitance coupled between a high voltage node and ground, a laser diode having an anode coupled to the high voltage node and a cathode coupled to an output node, and a current source coupled between the output node and ground. The current source turns on based on assertion of a trigger signal and sinks current from the capacitance to ground to thereby cause the laser diode to lase, and turns off based on deassertion of the trigger signal. A clamping circuit is coupled between the output node and the high voltage node, and clamps voltage at the output node occurring when the current source switches off.

A circuit includes a first transistor and a second transistor having respective control terminals coupled to receive first and second bias voltages. A first electronic switch is coupled in series with, and between current paths of the first and second transistors to provide an output current line between a circuit output node and ground. A second electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between a bias node and a charge transfer node in the output current line. A third electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between the charge transfer node and the control terminal of the second transistor.

Current steering circuit, corresponding device, system and method

A delay locked loop includes a control loop receiving reference and feedback clock signals, and generating biasing voltages therefrom. A delay chain receives the reference clock signal and generates N successively delayed versions thereof, each at a successive tap thereof. The Nth delayed version is the feedback clock signal. The control loop has a phase detector asserting an up signal when a phase of the feedback clock signal lags that of the reference clock signal, asserting a down signal when the phase of the feedback clock signal leads that of the reference clock signal. A digital filtering block compares a number of assertions of the up signal during the period of the reference clock signal to those of the down signal, and asserts an up or down command signal based thereupon. A biasing voltage generation circuit receives the up and down command signals and generates the biasing voltages therefrom.

Growing community of inventors

Leuven, Belgium

Alireza Tajfar