Intel Corporation

Alireza Sarabi

Robert L Farrell

Raymond Scott Tetrick

Steven D Kassel

Edwin L Jacks, Jr

Sudarshan Balachandran

John Beaston

A high speed local synchronous bus is disclosed for coupling processors within a multi-processor system such that local memory and secondary processing resources may be accessed without impacting data traffic along the bus. The local bus employs a message control method and apparatus which includes the ability to assert a WAIT signal when the processing resource is replying to a request. By asserting the WAIT signal all other operations on the bus are delayed until the transfer is complete. The use of the WAIT signal enables a device operating at a different speed from the primary processing resource to respond across the bus in a manner that is synchronized to the clock speed of the primary processing resource.

High speed synchronous/asynchronous local bus and data transfer method

A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as 'agents') to permit the exchange of data and messages at high speed using a minimum of 'handshake' events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.

High speed parallel bus and data transfer method

Growing community of inventors

Hillsboro, OR, United States of America

Alireza Sarabi