Imec Vzw

Katholieke Universiteit Leuven

AliReza Alian

Anne S Verhulst

Devin Verreck

Salim El Kazzi

Mohammad Ali Pourghaderi

The disclosed technology relates generally to semiconductor devices, and more particularly to field-effect transistors (FETs) comprising nanostructures, such as nanowires, fins, and two dimensional materials. In an aspect, a FET device comprises a substrate having an insulating surface and a vertical structure extending in a direction substantially perpendicular to the insulating surface, where the vertical structure has at least outer surfaces formed of an insulating material. The FET device additionally includes a thin layer of two-dimensional (2D) material enveloping the vertical structure and at least part of the insulating surface. The FET device additionally includes two electrodes in electrical contact with the thin layer of 2D material, where one of the electrodes is formed on top of the vertical structure. The FET device additionally includes a control electrode configured to apply an electric field across the thin layer of 2D material to cause a change in the conductivity of the thin layer of 2D material. The FET device further includes at least one stack of materials configured to provide different regions of band bending in the thin layer of 2D material by capacitive coupling.

Two dimensional field effect transistors

A Tunnel Field-Effect Transistor (TFET) is provided comprising a source-channel-drain structure of a semiconducting material. The source-channel-drain structure comprises a source region being n-type or p-type doped, a drain region oppositely doped than the source region and an intrinsic or lowly doped channel region situated between the source region and the drain region. The TFET further comprises a reference gate structure covering the channel region and a source-side gate structure aside of the reference gate structure wherein the work function and/or electrostatic potential of the source-side gate structure and the reference work function and/or electrostatic potential of the reference gate structure are selected for allowing the tunneling mechanism of the TFET device in operation to occur at the interface or interface region between the source-side gate structure and the reference gate structure in the channel region.

Multi-gate tunnel field-effect transistor (TFET)

A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.

Growing community of inventors

Heverlee, Belgium

AliReza Alian