Texas Instruments Corporation

Aline Claude Sadate

Christopher T Maxwell

Nakshatra S Gajbhiye

William E Grose

James Craig Spurlin

Wenliang Chen

John Mitchell Perry

Richard Turkson

Mustapha El-Markhi

Conventionally, current detection in load switches is implemented by monitoring the voltage across a small value sense resistor in series with the load switch, where the differential voltage across is applied to a comparator to generate a control signal corresponding to a light load condition, a normal load condition, or an over-load condition. Detecting the light load condition, however, can be difficult to determine using this arrangement due to the low differential voltage. Here, however, a integrated circuit (IC) is provided that employs an internal voltage supply and comparators to examine the load current to determine whether a light load condition is present, which does not suffer from the same problems.

Load switch having load detection

The disclosed transistor switching methodology enables independent control of transistor turn-on delay and slew rate, including charging, during a pre-charge period, a transistor control input to a threshold voltage Vwith a predetermined turn-on delay; and then charging, during a switch-on period, the transistor control input from Vto an operating point with a predetermined slew rate. This methodology is adaptable to load switching applications, for example, to control a high side/low side load switch such that, during the switch on period, the output voltage supplied to the load rises from zero volts to an operating load voltage with the predetermined slew rate. In one embodiment, I_delay and I_slew_rate currents are used to charge the transistor control input respectively during the pre-charge and switch-on periods. In another embodiment, the I-delay and I-slew rate currents are controlled by a replica switch with a control input coupled to the control input of a main switch, with the replica switch characterized by a threshold voltage substantially identical to the main switch threshold voltage V.

Transistor switch including independent control of turn-on and slew rate

An IC generally comprises enable pin, ground pin, input pin, output pin, load switch, control circuitry, and level shifter. Load switch is coupled between the input pin and output pin and receives a negative voltage through the input pin. The control circuitry is coupled to the enable pin, the ground pin, and the load switch and controls the load switch and uses ground pin as positive supply rail and input pin as an internal ground. Voltage applied to the input terminal is negative, enabling pulling of the gate of a transistor of a level shifter to ground turns transistor as 'on,' enabling a negative output signal to be provided through output pin VOUT. Therefore, the output signal (at output pin VOUT) can be ground (applied to the ground pin GND) when the transistor is 'off' and can be the negative voltage (applied to the input pin VIN) when transistor is &#x201c;on.&#x201d;

Load switch

Load switches are relatively common and in use with a variety of applications, and conventional load switches have been designed to have continually operating protection circuitry, which can consume a great deal of power. Here, a load switch integrated circuit (IC) is provided where a controller within the IC activates and deactivates various protection circuits in a sequence, allowing the protection circuit to protect the IC while also reducing power consumption.

Low power load switch with protection circuitry

A bias generator circuit with improved phase margin without RC compensation includes: a first transistor MP ; a second transistor MP coupled in parallel with the first transistor MP ; an amplifier A having a first input coupled to the first and second transistors MP and MP , and to a gate of the second transistor MP , and a second input coupled to a control voltage node VCTRL; a third transistor MN coupled in series with the first transistor MP ; a fourth transistor MN coupled in series with the third transistor MN and having a gate coupled to an output of the amplifier A ; a fifth transistor MP ; a sixth transistor MP coupled in parallel with the fifth transistor MP ; a seventh transistor MN coupled in series with the fifth transistor MP ; and an eighth transistor MN coupled in series with the seventh transistor MN and having a gate coupled to a gate of the fourth transistor MN . In order to maintain the bias generator stability for different biasing conditions, the feed-forward path is removed by diode connecting the second transistor MP instead of connecting the gate of the second transistor MP to the control voltage node VCTRL.

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Allen, TX, United States of America

Aline Claude Sadate