Motorola Corporation

Alick Einav

Moti Kurnick

Yehuda Volpert

Yehuda Shaik

Stefania Gandal

Yoram Horen

A clock system (2) for providing a system clock signal at a clock output (4) for use by a processing unit comprises a first oscillator circuit (6) which is enabled in response to a wake up signal provided by the processing unit to provide a first clock signal (RINGO CLOCK) at an output, and a second oscillator circuit (8) comprising a PLL (14) and an oscillator (16). The second oscillator (8) circuit provides a second clock signal (PLL CLOCK) and a lock signal (LOCKED) at first and second outputs respectively when the PLL is locked. The clock system (2) further comprises control circuitry (10) coupled to the output of the first oscillator circuit (6) and to the first and second outputs of the second oscillator circuit (8) for coupling the first clock signal (RINGO CLOCK) to the clock output (4) to provide the system clock signal or when the control circuitry (10) receives the lock signal (LOCKED) for coupling the second clock signal (PLL CLOCK) and not the first clock signal (RINGO CLOCK) to the clock output (4) to provide the system clock signal.

Clock system

A mantissa addition system (2) having a mantissa adder (6) for adding two mantissas provides an addition result a plurality of bits arranged in sub-groups. The mantissa addition system also has a flag generator which generates a flag for each sub-group: each flag having an active state when all the bits in the respective sub-group are zero and an inactive state when at least one of the bits in the respective sub-group is non-zero. A first detector (46) determines the most significant flag that has the inactive state and provides a first control signal representative of the detected most significant flag. A first shifter (40) shifts the groups of bits of the addition result in response to the first control signal so that the sub-group of bits corresponding to the detected most significant flag is the most significant group. A second detector (48) detects the most significant bit of the most significant sub-group of the shifted result that is non-zero and provides a second control signal representative of the detected most significant bit. A second shifter (42) shifts the plurality of bits of the shifted result in response to the second control signal so that the detected most significant non-zero bit is the most significant bit. The output (8) of the second shifter represents the normalised addition result. The shift information (N) is generated by logic means (52, 54) from the first and second control signals.

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Alick Einav