International Business Machines Corporation

Globalfoundries Inc.

Alicia Wang

K Paul Muller

Ethan Harrison Cannon

David F Heidel

Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of 'in-line' connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art 'side-by-side' transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in &#x201c;hardening&#x201d; of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.

In-line stacking of transistors for soft error rate hardening

A method for reducing single event upsets in an integrated circuit includes the step of providing a plurality of levels within the integrated circuit, wherein the plurality of levels within the integrated circuit are in a stacked arrangement. The method also includes the step of providing a plurality of metal fill patterns within each of the plurality of levels within the integrated circuit. The method further includes the step of placing the plurality of metal fill patterns within at least one of the plurality of levels in a pattern such that a line of sight towards an active silicon layer does not exist within the stacked arrangement of the plurality of levels, thereby increasingly absorbing ionizing radiation particles, and thereby reducing single event upsets in the integrated circuit.

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Wappingers Falls, NY, United States of America

Alicia Wang