Cadence Design Systems, Inc.

Ali Ulas Ilhan

Eric Harris Naviasky

A system and method are provided for selectively coupled parasitic compensation for voltage offset in an electronic circuit. At least one compensation cell is coupled to an input stage for the circuit. The compensation cell includes an isolation node disposed in spaced manner from control and sampling nodes defined by the input stage. The isolation node is configured to form first and second parasitic capacitances respectively with the control and sampling nodes during system operation. An offset switch is coupled to the isolation node and selectively set between first and second switching states. The offset switch selectively either maintains or interrupts a series coupling of the first and second parasitic capacitances between the control and sampling nodes; and, the sampling node is thereby adaptively adjusted in voltage by a predetermined portion of a control signal applied to the control node.

System and method for selectively coupled parasitic compensation for input referred voltage offset in electronic circuit

In a clock recovery system, a phase detector detects a phase error in an incoming data signal, which it outputs as a differential pair of voltage signals representing positive and negative errors, respectively. A proportional filter generates a proportional offset from the phase error, also as a differential pair of voltage signals. An integral filter generates an integral offset from the proportional offset, using positive and negative voltage controlled oscillators to generate oscillating integral offset signals, and an accumulator to increment or decrement a digital counter for each cycle of the integral offset signals. A first, fractional phase interpolator operating over a ninety-degree range adjusts the phase of an initial clock signal to generate an intermediate clock signal, according to the proportional offset. A second phase interpolator adjusts the phase of the intermediate clock signal to generate an adjusted clock signal, according to the integral offset.

Hybrid analog/digital clock recovery system

A system and method are provided for boosting a selective portion of a drive signal for chip-to-chip transmission across an interconnection interface. The system includes a driver unit generating a drive signal responsive to an input data signal. The drive signal is provided on to at least one output node for transmission through the device interconnection interface, and defines a peak amplitude during a drive period. A boosting unit is coupled to the driver unit for selectively boosting a portion of the drive signal. The boosting unit actuates responsive to the input data signal to selectively apply a boost signal in self-timed manner to the drive signal, so as to thereby augment the drive signal in amplitude over a selected portion of the drive period thereof. In this manner, the boosting unit maintains the peak amplitude of the drive signal at or above a predetermined level throughout the drive period.

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Elkridge, MD, United States of America

Ali Ulas Ilhan