Other

Ali Tasdighi Far

Jerry M Collings

Michael C Shebanow

Methods for performing mixed-mode Multiply-Accumulate (MAC) functions in an integrated circuit (IC) are disclosed. By performing part of the MAC operation spatially and in parallel, and part of it temporally and serially, the number of MAC operations can be programmed in the serial/temporal MAC segment as a multiple of the parallel/spatial MAC segment. Such a trait provides a degree of flexibility in programming the mixed-mode MAC function. A Programmable-Hybrid-Accumulation (PHA) method, performs the accumulation function of the MAC IC, by transforming the accumulation signal to a hybrid accumulation signal. The hybrid accumulation signal is comprised of a Most-Significant-Portion (MSP) and a Least-Significant-Portion (LSP), wherein the portions of the hybrid accumulation signal can be programmed in accordance with cost-performance objectives of an end application. Transforming the accumulated signal to a hybrid signal, and utilizing the PHA method, enables keeping the signal magnitudes bounded which prevent signal over-flow constraints while accumulation cycles proceed. Arranging a mixed-signal MAC in accordance with the PHA method can, among other benefits, help to limit the peak-to-peak analog signal swings which enhances performance attributes such as lower current consumption, faster speed, lower power supply voltage, and a wider signal accumulation range before power supply operating head-room conditions are breached.

Hybrid accumulation method in multiply-accumulate for machine learning

Methods of performing mixed-signal/analog multiply-accumulate (MAC) operations used for matrix multiplication in fully connected artificial neural networks in integrated circuits (IC) are described in this disclosure having traits such as: (1) inherently fast and efficient for approximate computing due to current-mode signal processing where summation is performed by simply coupling wires, (2) free from noisy and power hungry clocks with asynchronous fully-connected operations, (3) saving on silicon area and power consumption for requiring neither any data-converters nor any memory for intermediate activation signals, (4) reduced dynamic power consumption due to Compute-In-Memory operations, (5) avoiding over-flow conditions along key signals paths and lowering power consumption by training MACs in neural networks in such a manner that the population and or combinations of multi-quadrant activation signals and multi-quadrant weight signals follow a programmable statistical distribution profile, (6) programmable current consumption versus degree of precision/approximate computing, (7) suitable for 'always-on' operations and capable of 'self power-off', (8) inherently simple arrangement for non-linear activation operations such as Rectified Linear Unit, ReLu, and (9) manufacturable on main-stream, low cost, and lagging edge standard digital CMOS process requiring neither any resistors nor any capacitors.

Asynchronous analog accelerator for fully connected artificial neural networks

Digital approximate multipliers (aMULT) utilizing interpolative apparatuses, circuits, and methods are described in this disclosure. The disclosed aMULT interpolative methods can be arranged or programmed to operate asynchronously and or synchronously. For applications where less precision is acceptable, fewer interpolations can yield less precise multiplication results, while such approximate multiplication can be computed faster and at lower power consumption. Conversely, for applications where higher precision is required, more interpolations can generate more precise multiplication results. As such, by utilizing the disclosed aMULT method, the resolution and precision objectives of an approximate multiplication function can be pre-programmed or adjusted real-time and or on the fly, which enables optimizing for different and flexible power consumption and speed of multiplication, in addition to enabling the optimization of an approximate multiplier's die size and cost in accordance with cost-performance objectives.

Digital approximate multipliers for machine learning and artificial intelligence applications

Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.

Current-mode analog multipliers for artificial intelligence

Digital approximate squarer (aSQR)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed aSQR methods can operate asynchronously and or synchronously. For applications where low precisions is acceptable, fewer interpolations can yield less precise square approximation, which can be computed faster and with lower power consumption. Conversely, for applications where higher precision are required, more interpolations steps can generate more precise square approximation. By utilizing the disclosed aSQR method, precision objectives of a squarer approximation function can be programmed real-time and on the fly, which enables optimizing for power consumption and speed of squaring, in addition to optimize for the approximate squarer's die size and cost.

Digital approximate squarer for machine learning

Current-mode analog multiply-accumulate circuits for artificial intelligence

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers, and MACs. Typically, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers, and MACs increase, usually the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications. Moreover, the multipliers and MACs disclosed in this invention can be placed near conventional CMOS memory cells, such as Static-Random-Access-Memory (SRAM) or Electrically Programmable Read-Only Memory (EPROM) or Electrically Erasable Programmable Read-Only Memory (EPROM), which facilitates In-Memory-Compute (IMC) and or near-memory-compute (NMC), that can further reduce dynamic power consumption.

Current-mode mixed-signal SRAM based compute-in-memory for low power machine learning

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

Approximate nonlinear digital data conversion for small size multiply-accumulate in artificial intelligence

Methods of performing mixed-signal current-mode multiply-accumulate (MAC) operations for binarized neural networks in an integrated circuit are described in this disclosure. While digital machine learning circuits are fast, scalable, and programmable, they typically require bleeding-edge deep sub-micron manufacturing, consume high currents, and they reside in the cloud, which can exhibit long latency, and not meet private and safety requirements of some applications. Digital machine learning circuits also tend to be pricy given that machine learning digital chips typically require expensive tooling and wafer fabrication associated with advanced bleeding-edge deep sub-micron semiconductor manufacturing. This disclosure utilizes mixed-signal current mode signal processing for machine learning binarized neural networks (BNN), including Compute-In-Memory (CIM), which can enable on-or-near-device machine learning and or on sensor machine learning chips to operate more privately, more securely, with low power and low latency, asynchronously, and be manufacturable on non-advanced standard sub-micron fabrication (with node portability), that are more mature and rugged with lower costs. An example of enabling features of this disclosure is as follows: to save power in an 'always-on' setting, reduce chip costs, process signals asynchronously, and reduce dynamic power consumption. Current mode signal processing is utilized in combination with CIM (to further reduce dynamic power consumption associated with read/write cycles in and out of memory) for bitwise counting of plurality of logic state '1' of plurality of XOR outputs for MAC arithmetic in BNNs.

Current mode multiply-accumulate for compute in memory binarized neural networks

Multipliers, Multiply-Accumulate (MAC), and Square-Accumulate (SAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers, MACs, and SACs. Generally, digital multipliers, MACs, and SACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers, MACs, and SACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers, MACs, and SACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

Approximate mixed-mode square-accumulate for small area machine learning

Compact high-speed multi-channel current-mode data-converters for artificial neural networks

Single-stage and multiple-stage current-mode Analog-to-Digital converters (iADC)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed iADCs can operate asynchronously and be free from the digital clock noise, which also lowers dynamic power consumption, and reduces circuitry overhead associated with free running clocks. For their pseudo-flash operations, the disclosed iADCs do not require their input current signals to be replicated which saves area, lowers power consumption, and improves accuracy. Moreover, the disclosed methods of multi-staging of iADCs increase their resolutions while keeping current consumption and die size (cost) low. The iADC's asynchronous topology facilitates decoupling analog-computations from digital-computations, which helps reduce glitch, and facilitates gradual degradation (instead of an abrupt drop) of iADC's accuracy with increased input current signal frequency. The iADCs can be arranged with minimal digital circuitry (i.e., be digital-light), thereby saving on die size and dynamic power consumption.

Glitch free current mode analog to digital converters for artificial intelligence

Floating current-mode digital-to-analog-converters for small multipliers in artificial intelligence

Analog multipliers circuits can provide signal processing asynchronously and clock free and with low power consumptions, which can be advantageous, including in emerging mobile, portable, and at edge or near sensor artificial intelligence (AI) and machine learning (ML) applications. As such, analog multipliers can process signals memory-free in AI and ML applications, which avoids the power consumption and latency delays attributed to memory read-write cycles in conventional AI and ML digital processors. Based on standard digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of multi-quadrant current-mode analog multiplier (iMULT) circuits that can be utilized in current-mode multiply-accumulate (iMAC) circuits and artificial neural network (ANN) end-applications that require high-volumes, low costs, medium precision, low power consumptions, and clock free asynchronous signal processing.

Growing community of inventors

San Jose, CA, United States of America

Ali Tasdighi Far