Qualcomm Incorporated

Intel Corporation

Ali Taha

Yanru Li

Dexter Tamio Chun

Mohit Narang

Chih-Ping Hsu

Amit Mahajan

Chia-Hung Sophia Kuo

Amy Derbyshire

Hector Freires Corleto

William Zand

James W Tschanz

Robert F Kwasnick

Amer Catovic

Rahul Khanna

Thomas Klingenbrunn

Michael Lee McCloud

Todd Robert Sutton

Francis M Ngai

Francis Ming-Meng Ngai

Prashanth Akula

Rajat Mittal

Jeffrey Gemar

Haw-Jing Lo

Suresh Sugumar

Eric Ian Mikuteit

Vivek Venkatesh Ramachandran

Shawn C Morrison

Mohammad Tamjidi

Tao Xue

Hardik M Patel

Rahul Kashyap

Vipul Gandhi

Phani Babu Giddi

David Coronel

Xin Kang

Eric Mikuteit

Hector Corleto

Methods, apparatus, systems and articles of manufacture are disclosed to optimize a guard band of a hardware resource. An example apparatus includes at least one storage device, and at least one processor to execute instructions to identify a phase of a workload based on an output from a machine-learning model, the phase based on a utilization of one or more hardware resources, and based on the phase, control a guard band of a first hardware resource of the one or more hardware resources.

Methods and apparatus to optimize a guard band of a hardware resource

Embodiments of apparatuses and methods for dynamic prioritization of interconnect traffic in a system-on-chip are described. In an embodiment, an apparatus includes first circuitry to use a first weight value to weight operating system priority information to generate a first weighted priority value, second circuitry to use a second weight value to weight system-on-chip (SoC) hardware priority information to generate a second weighted priority value, third circuitry to sum the first weighted priority value and the second weighted priority value to generate a quality of service (QoS) value for an SoC interconnect transaction, and an arbiter to use the QoS value to prioritize the SoC interconnect transaction on an SoC interconnect.

Dynamic prioritization of system-on-chip interconnect traffic using information from an operating system and hardware

Embodiments of the present disclosure relate to an apparatus, comprising a first memory controller, to receive a signal from a component coupled with the first memory controller, where the signal indicates that data is to bypass a volatile memory device coupled with the first memory controller and be written to a byte-addressable write-in-place persistent memory device coupled with the first memory controller; determine, in response to the received signal, whether a write buffer in a second memory controller, coupled with the first memory controller, is empty; direct, if the write buffer is empty, the data to the write buffer for temporary storage prior to storage in the persistent memory device, to bypass the volatile memory device; and direct, if the write buffer is not empty, the data to the volatile memory device.

Bypassing cache memory in a write transaction in a system with multi-level memory

Provided are an apparatus and method to cache data in a first memory that is stored in a second memory. At least one read-with-invalidate command is received to read and invalidate at least one portion of a cache line having modified data. The cache line having modified data is invalidated in response to receipt of read-with-invalidate commands for less than all of the portions of the cache line.

Read-with-invalidate modified data in a cache line in a cache memory

A method includes initiating a transition from an operating mode to a sleep mode at an electronic device that includes a volatile memory and a non-volatile memory. In response to the initiating, data is copied from the volatile memory to the non-volatile memory and a portion of the volatile memory is disabled. Another method includes determining that a low performance mode condition is satisfied at an electronic device that includes a volatile memory that stores a first copy of read-only data and a non-volatile memory that stores a second copy of the read-only data. A memory mapping of the read-only data is updated from the volatile memory to the non-volatile memory. A portion of the volatile memory that stores the first copy is disabled and access of the read-only data is directed to the non-volatile memory instead of the volatile memory.

Reducing power consumption of volatile memory via use of non-volatile memory

An apparatus includes a first circuit and a second circuit sharing an instruction stream. A voltage controller circuit is configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream. In another aspect, a method of operating a power management function is presented. The method includes providing an instruction stream for a first circuit and a second circuit and providing selectively an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream.

Processor power management responsive to a sequence of an instruction stream

Methods and apparatuses for memory power reduction are provided. The apparatus determines whether to store data into a DRAM or an NVRAM during an idle state of a processor based on power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by the processor, based on power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on a duty cycle associated with current drawn in a first power state and a second power state in association with the data. The NVRAM is a type of non-volatile random-access memory other than flash memory. The processor stores the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM.

Methods and apparatuses for memory power reduction

A power management technique is provided that operates with regard to a dynamic sleep threshold voltage. If a device's battery voltage is greater than the dynamic sleep threshold voltage, a voltage rail for the device is collapsed during a sleep mode for the device. Conversely, if the battery voltage is less than the dynamic sleep threshold voltage, the voltage rail is sourced during the sleep mode for the device.

Dynamic sleep mode based upon battery charge

A method and system for managing electrical current within a portable computing device ('PCD') includes assigning a priority to two or more communications supported by the PCD. A present level of a power supply for the PCD may be monitored by a communications power ('CP') manager module. Next, the CP manager module may determine if the two or more communications may be transmitted at the present level of the power supply. If the two or more communications cannot be transmitted at the present level of the power supply, then the CP manager module may determine if a timing of at least one of the communications may be adjusted. The CP manager module may also determine a theoretical power level adjustment for at least one of the communications. The two or more communications may be transmitted with any calculated timing off sets and power level adjustments.

Managing electrical current in a portable computing device when two or more communications overlap in drawing power during a transmission

Apparatus and methods for power control management in a user equipment (UE) include establishing a first call and a second call at the UE, wherein the first call is associated with a first subscription and the second call is associated with a second subscription. Further, the apparatus and methods include determining concurrency of the first call and the second call. The apparatus and methods also includes adjusting a power level or operating frequency associated with at least one UE component based on determining the concurrency of the first call and the second call.

Methods and apparatuses for preemptive battery voltage management in multi-SIM mobile devices

Various embodiments of methods and systems for hardware ('HW') based dynamic memory management in a portable computing device ('PCD') are disclosed. One exemplary method includes generating a lookup table (&#x201c;LUT&#x201d;) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.

System and method for dynamic memory power management

Techniques for performing searches by a user equipment (UE) are described. The UE may camp on a serving cell for a first radio access technology (RAT) (e.g., GSM) and may periodically perform searches for a second RAT (e.g., WCDMA). In an aspect, the UE may vary the rate of searches for the second RAT based on received signal levels for the first and second RATs. The UE may determine a difference between the received signal levels for the two RATs, compare the difference against at least one threshold, and select a search rate associated with a range within which the difference falls as the rate of searches for the second RAT. In another aspect, the UE may control certain aspects of searches (e.g., determine whether or not to perform searches or the rate of searches) for the second RAT by considering the frequency bands for the two RATs.

Method and apparatus for performing inter-system searches in idle mode

Techniques for operating a diversity receiver are described. A user equipment (UE) may include (i) a first receive chain having an equalizer and a first rake receiver and (ii) a second receive chain having a second rake receiver. The UE may support (i) a first mode in which only the equalizer is used to process a received transmission and (ii) a second mode in which both rake receivers are used to process the received transmission. The UE may determine a first performance metric for the first mode (e.g., based on the performance of the equalizer) and a second performance metric for the second mode (e.g., based on the performance of both rake receivers or only the first rake receiver). The UE may select the first or second mode based on the performance metrics and may power down the second receive chain if the first mode is selected.

Method and apparatus for operating a diversity receiver with an equalizer and a rake receiver

Methods and apparatuses are presented for sleep optimization based on system information block SIB scheduling. A method for invoking sleep states within user equipment (UE) is presented. The method includes decoding a broadcast control channel with a cell, determining a System Information Block (SIB) schedule associated with the cell, determining a sleep time interval based upon the SIB schedule, and placing the UE in a sleep state using the sleep time intervals. An apparatus for invoking sleep states within UE is presented. The apparatus includes logic configured to decode a broadcast control channel with a cell, logic configured to determine a SIB schedule associated with the cell, logic configured to determine a sleep time interval based upon the SIB schedule, and logic configured to place the UE in a sleep state using the sleep time intervals.

Sleep optimization based on system information block scheduling

In a Universal Mobile Telecommunications (UMTS) system, a mobile device reads scheduling information for uplink interference (SIB7) from a Master Information Block, broadcasted on the Broadcast Channel (BCCH). The UE wakes up from the sleep during its periodic paging occasions and reads the paging indicator channel (PICH). If the UE needs to read the PCH, then the UE computes the timing of the next broadcast of SIB7 using the scheduling information broadcast in the MIB on BCCH. Knowing the timing of the next SIB7, the UE can determine if there is an overlap. If overlap is detected, the mobile device demodulates both the paging channel carried by the Secondary Common Control Physical Channel (S-CCPCH) and the broadcast channel carried by the Primary CCPCH, avoiding a mobile-terminated (MT) call setup delay by waiting for the next SIB7 broadcast, which depending upon a SIB7 repetition ranges from 360 msec to 2.56 seconds.

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San Diego, CA, United States of America

Ali Taha