Taiwan Semiconductor Manufacturing Comp. Ltd.

Ali Taghvaei

Atul Katoch

Sanjeev Kumar Jain

Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory cell, a precharge circuit, a reset voltage control circuit, and a logic control circuit. In one aspect, the precharge circuit is configured to set a voltage of the bit line to a first voltage level. In one aspect, the reset voltage control circuit includes a transistor coupled to the bit line to set the voltage of the bit line to a second voltage level. The transistor can be arranged or operate as a diode. In one aspect, the logic control circuit is configured to cause the reset voltage control circuit to set the voltage of the bit line to the second voltage level during a reset phase and cause the precharge circuit to set the voltage of the bit line to the first voltage level during a precharge phase after the reset phase.

Memory device with reset voltage control

Word-line drivers, memories, and methods of operating word-line drivers are provided. A word-line driver coupled to an array of memory cells includes a decoder powered by a first power supply. The decoder is configured to decode an address to provide a plurality of word-line signals. The word-line driver also includes a plurality of output stages powered by a second power supply that is different than the first power supply. Each of the output stages includes a first transistor having a gate controlled by a first control signal and an inverter. The inverter is coupled between the first transistor and a ground and has an input coupled to the decoder to receive one of the word-line signals. The word-line driver also includes pull-down circuitry coupled between the gates of the first transistors and the ground and activated by a second control signal.

Word-line driver and method of operating a word-line driver

A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.

SRAM with local bit line, input/output circuit, and global bit line

A memory array having a first port and a second port is disclosed. The memory array includes: a first memory cell, wherein access to the first memory cell through the first port is controlled by a first word line, and access to the first memory cell through the second port is controlled by a second word line; a second memory cell, wherein access to the second memory cell through the first port is controlled by the first word line, and access to the second memory cell through the second port is controlled by the second word line; and a disturb detector, used to generate a disturb detected signal for indicating whether the first memory cell and the second memory cell are accessed at a same time. A memory array having a write assistor is also disclosed.

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Ali Taghvaei