Fujitsu Corporation

Mosaid Technologies Corporation

Other

University of Toronto

Northern Telecom Limited

Analog Devices Global

Ali Sheikholeslami

Hirotaka Tamura

Igor Arsovski

Shoichi Masui

Takahiro Hanyu

Joshua Liang

P Glenn Gulak

Hajime Shibata

Sanroku Tsukamoto

Takayuki Shibasaki

Hisakatsu Yamaguchi

Kouichi Kanda

Trevor Clifford Caldwell

Donald W Paterson

Yuuki Ogata

Zhao Li

Wahid Rahman

Trevis Chandler

Yadollah Eslami

Mohammad Bagherbeik

Mehrdad Malekmohammadi

Keivan Dabiri

Trevor Caldwell

According to an aspect of an embodiment, operations may include obtaining a first fixed temperature and a second fixed temperature of a replica exchange Markov Chain Monte Carlo (MCMC) process used to solve an optimization problem associated with a system, and obtaining a plurality of replicas of the system. The operations may also include obtaining a target swap acceptance probability with respect to swapping, during the replica exchange MCMC process, between replicas that correspond to adjacently ordered temperatures of a set of temperatures between the first fixed temperature and the second fixed temperature. The operations may include determining a respective average swap acceptance probability with respect to one or more respective adjacent pairs of temperatures. Further, the operations may include adjusting one or more of the variable temperatures based on a relationship between the target swap acceptance probability and each of one or more of the respective swap acceptance probabilities.

Automatic adjustment of replica exchange

According to an aspect of an embodiment, operations may include obtaining a first matrix associated with an optimization problem associated with a system and obtaining a second matrix associated with the optimization problem. The operations may include obtaining a local field matrix that indicates interactions between the variables of the system as influenced by their respective weights. The operations may include updating the local field matrix. Updating the local field matrix may include performing arithmetic operations with respect to a first portion of the first matrix and a second portion of the second matrix that correspond to a third portion of the local field matrix that corresponds to the one or more variables. The operations may include updating an energy value of the system based on the updated local field matrix and determining a solution to the optimization problem based on the energy value.

System local field matrix updates

A jitter measurement circuit includes an addition circuit to add a digital rectangular signal to an adjustment signal generated by a circuit that generates a first error signal based on a phase difference between a first clock signal or a data signal on which the first clock signal is superimposed and a second clock signal and generates the adjustment signal by filtering the first error signal, and a calculation circuit to calculate a first correlation value for representing an autocorrelation of the first error signal when the rectangular signal is not added to the adjustment signal, and a second correlation value for representing the autocorrelation when the rectangular signal is added to the adjustment signal, based on the first error signal and a second error signal obtained by delaying the first error signal by a variable delay amount, and output the first correlation value and the second correlation value.

Jitter measurement circuit and jitter measurement system

A serial-parallel conversion circuit includes: a phase detector that outputs a first phase detection signal indicating whether a phase of a clock signal is advance or behind, a signal amplifying circuit that amplifies the first phase detection signal with a gain so as to output a second phase detection signal; a control loop that adjusts the phase of the clock signal based on the second phase detection signal; an autocorrelation circuit that generates an autocorrelation value based on the first phase detection signal and a set delay amount, and outputs an autocorrelation signal indicating the autocorrelation value; a gain adjusting circuit that adjusts the gain in such a manner that the autocorrelation value matches a target correlation value; and a delay-amount determination circuit that sets a delay amount corresponding to a peak value of an obtained autocorrelation value obtained when the autocorrelation value changes in an oscillatory manner.

Clock generating circuit, serial-parallel conversion circuit, and information processing device

A CDR circuit includes: a comparison circuit that receives data signal on which a first clock signal is superimposed, and outputs a comparison result obtained by comparing the data signal with three different threshold values at a timing synchronized with a second clock signal; a data pattern detection circuit that detects an occurrence of a data pattern, based on the comparison result; a frequency detection circuit that outputs, when an occurrence of the data pattern is detected, a detection result indicating whether a second frequency of the second clock signal is higher than a first frequency of the first clock signal; an adjustment circuit that outputs, based on the detection result, an adjustment signal for adjusting a phase of the second clock signal and the second frequency; and an oscillator circuit that outputs the second clock signal with the phase and the second frequency adjusted, based on the adjustment signal.

CDR circuit and receiving circuit

A system may include a detector, a controller, a shuffler, and a processor. The detector may detect a signal. The controller may control the shuffler based upon the signal. The shuffler may shuffle a plurality of channels at the input of a plurality of processing elements of the processor based upon the signal. The processor may process the signal according to the plurality of channels as configured by the shuffler.

Adaptive element shuffler

A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In other words, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits. Significant power reduction without compromising search speed is realized since matchlines carrying a match result are provided with the maximum amount of current.

Low power match-line sensing circuit

A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits. Significant power reduction without compromising search speed is realized since matchlines carrying a match result are provided with the maximum amount of current.

For a predetermined period from the start of a read operation, an electric current is fed to bit lines connected with memory cells so that ferroelectric capacitors of the memory cells are charged. The voltage change of the bit lines are different according to the logic values of data stored in the ferroelectric capacitors. Therefore, the logic value stored in the memory cells can be detected as a time difference. Even if the voltage change of the bit lines is small, the time difference can be reliably generated. Even in case the residual dielectric polarization value of the ferroelectric capacitor is low, therefore, the data can be reliably read from the memory cells. In short, the read margin of data can be better improved than in the case where the logic value of data is detected with a voltage difference.

Ferroelectric memory

Mismatch-dependent power allocation technique for match-line sensing in content-addressable memories

Upon reading data from a memory cell, first and second bit lines are precharged beforehand at a grounding voltage. Then, at a start of the reading, a predetermined amount of direct-current bias electricity is supplied to the first and second bit lines for a predetermined period of time by a direct-current bias electricity supply circuit. Thereafter, a sense amplifier is activated.

Ferroelectric memory supplying predetermined amount of direct-current bias electricity to first and second bit lines upon reading data from memory cell

Binary and multiple-valued nonvolatile content addressable memories (NVCAMs) use ferroelectric capacitors as nonvolatile storage elements. The operation of the NVCAMs is accessed either in serial or in parallel. In a 2-bit NVCAM of a parallel access structure, search operation is performed by a simultaneous access to a 4-level polarization of the ferroelectric capacitor. The total number of search operations is reduced.

Nonvolatile content addressable memory

Binary and multiple-valued nonvolatile content addressable memories (NVCAMs) use ferroelectric capacitors as nonvolatile storage elements. The operation of the NVCAMs is accessed either in serial or in parallel. In a 2-bit NVCAM of a parallel access structure, search operation is performed by a simultaneous access a 4-level polarization of the ferroelectric capacitor. The total number of search operations is reduced.

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Toronto, Canada

Ali Sheikholeslami