Intel Corporation

Ali S Oztaskin

Leonard W Cross

Hemal Vinodchandra Shah

Gary Tsao

John L Allen

Brian K Langendorf

Bruce A Young

George R Hayek

Bill A Munson

David R Jackson

Peter B Bloch

Arturo L Arizpe

Mark W Miller

Ioannis T Schoinas

Vadim Makhervaks

Rajesh Sankaran Madukkarumukumana

Kenneth G Keels

Scott D Hahn

Brian S Hausauer

Robert A Jacobs

Greg J Regnier

Aniruddha Kundu

Raman Nayyar

Suvansh Krishan Kapur

Jeffrey F Harness

Greg D Cummings

Roger L Traylor

Ellen M Deleganes

Ganesh Murthy

Methods, apparatus and systems for reducing usage of Doorbell Rings in connection with RDMA operations. A portion of system memory is employed as a Memory-Mapped Input/Output (MMIO) address space configured to be accessed via a hardware networking device. A Send Queue (SQ) is stored in MMIO and is used to facilitate processing of Work Requests (WRs) that are written to SQ entries by software and read from the SQ via the hardware networking device. The software and logic in the hardware networking device employ pointers identifying locations in the SQ corresponding to a next write WR entry slot and last read WR entry slot that are implemented to enable WRs to be written to and read from the SQ during ongoing operations under which the SQ is not emptied such that doorbell rings to notify the hardware networking device that new WRs have been written to the SQ are not required.

Methods, apparatus and systems for facilitating RDMA operations with reduced doorbell rings

Provided are a method, system, and program for utilizing a virtualized data structure table such as an address translation and protection table (TPT), for example, in an I/O device. The virtualized data structure table has virtually contiguous data structures but not necessarily physically contiguous data structures in system memory. The data structure table may be accessed in a virtually contiguous manner. In the illustrated embodiment, the table is subdivided at a first hierarchal level into a plurality of virtually contiguous units or segments. Each unit or segment is in turn subdivided at a second hierarchal level into a plurality of virtually contiguous subunits, subsegments, pages or blocks. Each page or block is in turn subdivided at a third hierarchal level into a plurality of physically contiguous table entries. The data structure table may be accessed in a virtually contiguous manner utilizing a set of hierarchal data structure tables corresponding to the hierarchal levels of the data structure table.

Method, system, and program for utilizing a virtualized data structure table

In accordance with certain other techniques, doorbell information is received. A doorbell structure address is decoded from the doorbell information. A first protection domain identifier is determined from the doorbell structure address. A resource context of a data structure is determined from the doorbell information. The resource context at the doorbell address is read to determine a second protection domain identifier. The first protection domain identifier and the second protection domain identifier are compared to determine whether to update the resource context of the doorbell structure.

Doorbell mechanism using protection domains

An apparatus and method related to performing Remote Direct Memory Access Request ('RDMA') is presented. In one embodiment, the apparatus comprises Remote direct memory access ('RDMA') logic that executes a direct memory access (&#x201c;DMA&#x201d;) request from the remote peer. The apparatus further comprising a protection checking logic to verify a key and a target address in the DMA request and conversion logic to convert the target address to an input/output virtual address (&#x201c;IOVA&#x201d;) if the conversion is required. The IOVA is to be translated to the host physical address by an address translation unit at another hardware subsystem.

Method and apparatus by utilizing platform support for direct memory access remapping by remote DMA ('RDMA')-capable devices

In one embodiment, a method is provided. The method of this embodiment provides determining if a management queue can be created, and if a management queue can be created, allocating virtually contiguous memory to a management queue associated with a device, registering the management queue, and creating a management queue context.

Managing system memory resident device management queues

An apparatus and method for controlling data traffic flow and data ordering of packet data between one or more peripheral devices and a processor/memory combination by using a packet processing engine, located within an input-output hub (IOH). The IOH may include a packet processing engine, and a switch to route packet data between the one or more peripheral devices and the packet processing engine. The packet processing engine of the IOH may control data traffic flow and data ordering of the packet data to and from the one or more peripheral devices through the switch and also maintains flow and ordering to the processor/memory subsystem. The packet processing engine may be operable to perform packet processing operations, such as virtualization of a peripheral device or Transmission Control Protocol/Internet Protocol (TCP/IP) offload.

Transaction flow and ordering for a packet processing engine, located within an input-output hub

Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a state of an event data structure. The Input/Output device writes an event entry into the event data structure in response to determining that the event has occurred. After writing the event entry, the Input/Output device determines whether to generate an interrupt or not based on the state of the event data structure. Additionally provided are techniques for interrupt processing in which an I/O device driver determines that an interrupt has occurred. The I/O device driver reads an event entry in an event data structure in response to determining that the interrupt has occurred. The I/O device driver updates a state of a structure state indicator to enable/disable interrupts.

Interrupt system using event data structures

A flexible event monitoring counter apparatus and process are provided for a processor system including a plurality of nodes, each node having a processor and a portion of a total main memory of the processor system. One example of such a processor system is a Non-Uniform-Memory-Architecture (NUMA) system. In order to reduce the total number of counters necessary, the counter structure will track certain ones of a type of event which occur in the processor system, determined in accordance with a predetermined standard to be most interesting, while discarding other ones of the same type of event determined by the standard to be less interesting. In accordance with one embodiment, the type of event which is tracked or discarded can be page accesses to pages of the total main memory. The standard of most interesting events can be based on the pages which receive the most requests for remote access from a node other than the node where the requested page is located. The information regarding the most interesting events can be used, if desired, to make decisions regarding migration and/or replication of pages between the different nodes.

Flexible event monitoring counters in multi-node processor systems and process of operating the same

A computer system having an integrated bus bridge and memory controller circuit and method for enabling access to a shared memory with high bandwidth data streaming are disclosed. The integrated bus bridge and memory controller circuit performs a series of snoop ahead transactions over a first bus during access transactions to the shared memory that originate over a second bus and thereby enables high bandwidth data streaming on the second bus. The integrated bus bridge and memory controller circuit includes a peripheral write buffer that buffers write data received over the second bus and that stores a snoop done flag for the write data that indicates whether a corresponding snoop ahead transaction for the write data is complete. The integrated bus bridge and memory controller circuit further includes a peripheral read prefetch buffer that prefetches read data during read transactions over the second bus only after a corresponding snoop ahead transaction for the read data is complete.

Integrated bus bridge and memory controller that enables data streaming

An apparatus for managing power in an electronic device that receives the power from a bus is described. The apparatus comprises a clock enable circuit that disables a clock that generates nominal clock frequencies derived from raw frequencies output by an oscillator upon receiving a first signal. A time-wise independent time reference circuit is coupled to the clock enable circuit. The time-wise independent time reference circuit sends the first signal to the clock enable circuit a first predetermined period of time after receiving a signal to enter into a suspend state.

Method and apparatus for supporting power conservation operation modes

A method and device is provided for controlling access to a resource by a bus master over a bus coupling the bus master to the resource. The resource includes an intelligent component that controls the operation of the resource. A series of packets is transmitted over the bus between the bus master and the resource, at a transmission speed controlled by the bus master. A request/response logic in the resource controllably throttles transmissions of the packets at the resource, at specified time intervals. Each of the time intervals is set at a time period to assure sufficient time for the intelligent component to complete processing tasks contained in the packets.

Programmable and adaptive resource allocation device and resource use

A method and apparatus for draining video data from a planarized video buffer in a video camera. The method includes the steps of reading a first sequence of video data from a first plane of the planarized image buffer starting at a buffer address indicated by a first pointer, and then reading a second sequence of video data from a second plane of the planarized image buffer starting at a buffer address indicated by a second read pointer. The apparatus includes an address generation unit and a sequence counter. The address generation unit includes a number of read pointers each configured to indicate a memory location within a different data plane of a video buffer. The address unit is configured to address a sequence of memory locations in a video buffer starting at a location indicated by an active one of the read pointers. The sequence counter is configured to detect when a final memory location of the sequence of memory locations has been addressed by the address generation unit and, in response, to select a different one of the read pointers to be the active read pointer.

Method and apparatus for draining video data from a planarized video

A bridge logic takes write cycles that appear one at a time as an address followed by an associated data word on a host bus, detects consecutive addresses, and uses this information to create burst cycles on a peripheral control interface (PCI) bus that has protocols that allow burst cycles.

Host initiated PCI burst writes utilizing posted write buffers

Briefly, in accordance with one embodiment, an integrated circuit includes: electronic circuitry for transferring digital data signals along a digital data signal path between different clock timing domains. The clock timing domains have a common higher frequency source clock. A first clock timing domain clock signal has a relatively fixed phase and a second clock timing domain clock signal has a relatively varying phase. The electronic circuitry includes delay elements in clock signal paths associated with the digital data signal path so that along the digital data signal path, clock signals in different clock timing domains are respectively staggered for a relatively short time compared with a given cycle of the source clock. The electronic circuitry further includes a digital data signal path including a data value retention element to delay the transfer of digital data signals between different clock timing domains at selected times.

Method and apparatus for transferring signals between multiple clock

A bridge logic takes non-burst write cycles that appear one at a time as an address followed by an associated data word on a first bus, detects consecutive addresses, and uses this information to create burst cycles on a second bus that has protocols that allow burst cycles such as a Peripheral Component Interconnect (PCI) bus.

Growing community of inventors

Beaverton, OR, United States of America

Ali S Oztaskin