Apple Inc.

Ali Rabbani Rankouhi

Justin A Hensley

Jonathan M Redshaw

Luca O Iuliano

Christopher A Burns

Doron Rajwan

Steven John Fishwick

Ralph Clay Taylor

David A Gotwalt

Benjamin Bowman

Fergus W MacGarry

Terence M Potter

Yoong Chert Foo

Andrew M Havlir

Michael Andrew Mang

Richard Warren Schreyer

Mladen Wilder

Jason David Carroll

Max J Batley

Melissa L Velez

Ji Rao

Techniques are disclosed relating to distributing geometry work in a graphics processor. In some embodiments, multiple geometry pipelines are configured to process, in parallel, multiple segments of a set of geometry work. In some embodiments, control circuitry is configured to split operations from the set of graphics work into the multiple segments. This may include parsing a control stream for the set of graphics work to determine an initial work estimate based on numbers of primitives in different draw calls and adjusting the initial work estimate based on a complexity determination for the draw call.

Parse techniques for graphics workload distribution

Disclosed techniques relate to acceleration data structure for ray intersection testing. In some embodiments, storage circuitry stores node data for a spatially organized acceleration data structure, including to store the following node information for a given node: origin coordinates for the node and, for a given child node of multiple child nodes, child information that includes: quantized bounding region information for a bounding region corresponding to the child node, where the quantized bounding region information encodes bounding region coordinates as offsets relative to the origin coordinates. Traversal circuitry may traverse multiple nodes of the data structure and determine whether a ray intersects a bounding region indicated by given a node of the data structure based on the node information. Disclosed techniques may provide substantial improvements to performance, data size, and power consumption.

Node encoding for spatially-organized ray tracing acceleration data structure

Disclosed embodiments relate to controlling sets of graphics work (e.g., kicks) assigned to graphics processor circuitry. In some embodiments, tracking slot circuitry implements entries for multiple tracking slots. Slot manager circuitry may store, using an entry of the tracking slot circuitry, software-specified information for a set of graphics work, where the information includes: type of work, dependencies on other sets of graphics work, and location of data for the set of graphics work. The slot manager circuitry may prefetch, from the location and prior to allocating shader core resources for the set of graphics work, configuration register data for the set of graphics work. Control circuitry may program configuration registers for the set of graphics work using the prefetched data and initiate processing of the set of graphics work by the graphics processor circuitry according to the dependencies. Disclosed techniques may reduce kick-to-kick transition time, in some embodiments.

Kickslot manager circuitry for graphics processors

Disclosed techniques relate to work distribution in graphics processors. In some embodiments, an apparatus includes circuitry that implements a plurality of logical slots and a set of graphics processor sub-units that each implement multiple distributed hardware slots. The circuitry may determine different distribution rules for first and second sets of graphics work and map logical slots to distributed hardware slots based on the distribution rules. In various embodiments, disclosed techniques may advantageously distribute work efficiently across distributed shader processors for graphics kicks of various sizes.

Logical slot to hardware slot mapping for graphics processors

Disclosed techniques relate to forming single-instruction multiple-data (SIMD) groups during ray intersection traversal. In particular, ray intersection circuitry may include dedicated circuitry configured to traverse an acceleration data structure, but may dynamically form a SIMD group to transform ray coordinates when traversing from one level of the data structure to another. This may allow shader processors to execute the SIMD group to perform the transformation. Disclosed techniques may facilitate instancing of graphics models within the acceleration data structure.

SIMD group formation techniques during ray intersection traversal

Techniques are disclosed relating to a shared control bus for communicating between primary control circuitry and multiple distributed graphics processor units. In some embodiments, a set of multiple processor units includes first and second graphics processors, where the first and second graphics processors are coupled to access graphics data via respective memory interfaces. A shared workload distribution bus is used to transmit control data that specifies graphics work distribution to the multiple graphics processing units. The shared workload distribution bus may be arranged in a chain topology, e.g., to connect the workload distribution circuitry to the first graphics processor and connect the first graphics processor to the second graphics processor such that the workload distribution circuitry communicates with the second graphics processor via the shared workload distribution bus connection to the first graphics processor. Disclosed techniques may facilitate graphics work distribution for a scalable number of processors.

United states graphics processor techniques with split between workload distribution control data on shared control bus and corresponding graphics data on memory interfaces

Techniques are disclosed relating to ray intersection in the context of motion blur. In some embodiments, a graphics processor includes time-oblivious ray intersect circuitry configured to receive coordinates for a ray and traverse a bounding volume hierarchy (BVH) data structure based on the coordinates to determine whether the ray intersects with one or more bounding regions of a graphics space. In some embodiments, in response to reaching a temporal branch element of the BVH data structure, the ray intersect circuitry initiates a shader program that determines a sub-tree of the BVH data structure for further traversal by the ray intersection circuitry, where the sub-tree corresponds to a portion of a motion-blur interval in which the ray falls. This may provide accurate ray tracing for motion blur while reducing area and power consumption of intersect circuitry, relative to time-aware implementations.

Temporal split techniques for motion blur and ray intersection

Disclosed techniques relate to memory space management for graphics processing. In some embodiments, first and second graphics cores are configured to execute instructions for multiple threadgroups. In some embodiments, the threads groups include a first threadgroup with multiple single-instruction multiple-data (SIMD) groups configured to execute a first shader program and a second threadgroup with multiple SIMD groups configured to execute a second, different shader program. Control circuitry may be configured to provide access to data stored in memory circuitry according to a shader memory space. The shader memory space may be accessible to threadgroups executed by the first graphics shader core, including the first and second threadgroups, but is not accessible to threadgroups executed by the second graphics shader core. Disclosed techniques may reduce latency, increase bandwidth available to the shader, reduce coherency cost, or any combination thereof.

Graphics memory space for shader core

Disclosed techniques relate to primitive testing associated with ray intersection processing for ray tracing. In some embodiments, shader circuitry executes a first SIMD group that includes a ray intersect instruction for a set of rays. Ray intersect circuitry traverses, in response to the ray intersect instruction, multiple nodes in a spatially organized acceleration data structure (ADS). In response to reaching a node of the ADS that indicates one or more primitives, the apparatus forms a second SIMD group that executes one or more instructions to determine whether a set of rays that have reached the node intersect the one or more primitives. The shader circuitry may execute the first SIMD group to shade one or more primitives that are indicated as intersected based on results of execution of the second SIMD group. Thus, disclosed techniques may use both dedicated ray intersect circuitry and dynamically formed SIMD groups executed by shader processors to detect ray intersection.

SIMD group formation techniques for primitive testing associated with ray intersect traversal

Disclosed techniques relate to grouping rays during traversal of a spatially-organized acceleration data structure (e.g., a bounding volume hierarchy) for ray intersection processing. The grouping may provide temporal locality for accesses to bounding region data. In some embodiments, ray intersect circuitry is configured to group rays based on the node of the data structure that they target next. The ray intersect circuitry may select one or more groups of rays for issuance each clock cycle, e.g., to bounding region test circuitry.

Grouping techniques for ray intersection traversal

Disclosed techniques relate to ray intersection processing for ray tracing. In some embodiments, ray intersection circuitry traverses a spatially organized acceleration data structure and includes bounding region circuitry configured to test, in parallel, whether a ray intersects multiple different bounding regions indicated by a node of the data structure. Shader circuitry may execute a ray intersect instruction to invoke traversal by the ray intersect circuitry and the traversal may generate intersection results. The shader circuitry may shade intersected primitives based on the intersection results. Disclosed techniques that share processing between intersection circuitry and shader processors may improve performance, reduce power consumption, or both, relative to traditional techniques.

Ray intersect circuitry with parallel ray testing

Disclosed techniques relate to an acceleration data structure for ray intersection with a many-to-many mapping between bounding regions and primitives. In some embodiments, one or more graphics processors access data for multiple graphics primitives in a graphics scene and generate a spatially organized data structure. Some nodes of the data structure indicate graphics primitives and some nodes indicate coordinates of bounding regions in the graphics scene. In some embodiments, the spatially organized data structure includes a node with a bounding region for which multiple primitives are indicated as children and also includes a primitive for which multiple bounding regions are indicated as parents. Disclosed techniques may generate bounding regions that closely fit primitives, which may reduce primitive testing for ray tracing. This in turn may increase performance or reduce power consumption relative to traditional techniques.

Ray intersection data structure with many-to-many mapping between bounding regions and primitives

An apparatus includes a decoding circuit, and a communication bus that is configured to transfer a particular data payload and a control signal that indicates whether the particular data payload includes a mask value. The mask value is indicative of enabled and non-enabled data words in the particular data payload. The decoding circuit is configured to receive, from an encoding circuit via the communication bus, the particular data payload and the control signal. In response to a determination that the control signal indicates that the particular data payload does not include the mask value, the decoding circuit is configured to use a default value for the mask value, and to create an uncompressed data payload from the particular data payload using the default value, wherein the default value causes the decoding circuit to maintain positions of data words between the particular data payload and the uncompressed data payload.

Data-enable mask compression on a communication bus

An apparatus includes an encoding circuit, and a communication bus having conductive traces configured to transfer a data payload, including a control signal and up to a maximum number of data words. The encoding circuit is configured to receive an uncompressed data payload and a mask value, and to create, using the mask value, the control signal, the control signal indicative of whether the uncompressed data payload includes one or more non-enabled data words. In response to a determination that the control signal indicates that the uncompressed data payload includes one or more non-enabled data words, the encoding circuit is configured to create a compressed data payload from the uncompressed data payload, and to send, to a decoding circuit, the compressed data payload and the control signal via the plurality of conductive traces of the communication bus. The compressed data payload includes the mask value.

Growing community of inventors

St. Albans, United Kingdom

Ali Rabbani Rankouhi