Intel Corporation

Motorola Corporation

Ali R Farhang

Vivek K De

Muhammad M Khellah

Dinesh Somasekhar

Yibin Ye

Scott G Nogle

Gunjan H Pandya

Douglas A Guddat

Eric B Selvin

A SRAM memory cell comprising cross-coupled inverters, each cross-coupled inverter comprising a pull-up transistor, where the pull-up transistors are forward body biased during read operations. Forward body biasing improves the read stability of the memory cell. Other embodiments are described and claimed.

SRAM with forward body biasing to improve read cell stability

A new programmable weak write circuit is defined with the ability to perform SRAM weak write testing at multiple stress strength settings which track process variation. Prior art weak write test circuitry is designed to test a population of SRAM devices at a fixed weak write stress strength as determined by the best available pre-silicon design environmental factors. This design may over- or under-test SRAM cells for the target defects due to poor process tracking characteristics and may require multiple post-silicon design iterations to keep up with environmental changes following initial design. In the new circuit, multiple settings are designed in pre-silicon to account for the expected uncertainty in environmental factors. During post-silicon testing, a suitable stress setting is selected based on an acceptable or predetermined quality versus test yield tradeoff and its suitability is re-evaluated following any significant environmental changes to determine if a different stress setting is necessary.

Programmable weak write test mode

An output buffer circuit (20) has an output impedance that is adjustable. An external resistor (32) having a resistance that is a multiple of the desired output impedance is coupled to the output buffer circuit (20). A voltage across the resistor (32) is converted to a digital code using an analog-to-digital (A/D) converter (22). A digital code from the A/D converter (24) is used to adjust a resistance of a binary weighed transistor array (45) to match the resistance of the external resistor (32). A plurality of binary weighted output transistors (153, 154, 155) are selected in response to the digital code to adjust the output impedance to match the characteristic impedance of a load driven by the output buffer circuit (20). The output impedance is easily adjustable by changing the resistance of external resistor (32), allowing the output buffer circuit to drive various load impedances.

Buffer circuit having variable output impedance

Growing community of inventors

Beaverton, OR, United States of America

Ali R Farhang