Genesis Microchip Corporation

Tamiras Per Pte. Ltd., LLC

Cirrus Logic Inc.

Other

Megachips Technology America Corporation

Ali Noorbakhsh

David C Keene

John Lattanzi

Ram Chilukuri

Osamu Kobayashi

Tzoyao Chan

Chia-Lun Hang

Jih-Hsien Soong

Alan Osamu Kobayashi

Sujan Valiyaka Thomas

Detecting when the on-board power supply is powered on or off by an auto activity detection circuit by determining if the reference clock signal (T) is toggling, and, if the reference clock signal is toggling, then charging a capacitor to a high voltage in the auto activity detection circuit based on the toggling reference clock signal, and outputting an on-board power supply activity signal based upon the high voltage by the auto activity detection circuit indicative of whether or not the on-board power supply is active.

Automatic activity detection in a display controller

A DisplayPort (DP) High-bandwidth Digital Content Protection (HDCP) version converter that converts an HDCP content protection version from input to output includes a receiver and a transmitter. The receiver receives a serial bit stream transmitted from an upstream device, and decrypts link symbols of the received serial bit stream by use of a decryption unit. The transmitter encrypts, by use of an encryption unit, the link symbols decrypted by the receiver, and converts the encrypted link symbols into a serial bit stream and transmits the serial bit stream to a downstream device. The receiver and the transmitter have the same link configuration.

DP HDCP version converter

Detecting when the on-board power supply is powered on or off by an auto activity detection circuit by determining if the reference clock signal (T) is toggling and if the reference clock signal is toggling, then charging a capacitor to a high voltage in the auto activity detection circuit based on the toggling reference clock signal, and outputting an on-board power supply activity signal based upon the high voltage by the auto activity detection circuit indicative of whether or not the on-board power supply is active.

A display controller includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device that is always available for access by the data ports and/or the processor regardless of a power state of the display controller, a data buffer for storing EDID read from the memory device, and an arbitration circuit for arbitrating memory device access requests between the processor and a requesting data port wherein when the data buffer is not almost empty, then the arbitration circuit grants the processor access to the memory wherein when the data buffer is almost empty, then the arbitration circuit grants only the requesting data port access to them memory so as to replenish the data buffer with read EDID.

Arbitration for acquisition of extended display identification data (EDID)

A display controller coupled to a display device by way of a display interface and to a host device by way of a data port that includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device, and a bridge portion coupling the single memory device to the host device by way of the data port, wherein the bridge portion is always in a powered on state thereby providing access to the single memory device by the host device even when the display controller is in a powered off state such as during a boot up process when the display controller is in the powered off state.

Method for acquiring extended display identification data (EDID) in a powered down EDID compliant display controller

Virtual extended display information data (EDID) in a flat panel controller

In a VESA standard compliant display controller having a processor arranged to process executable instructions and associated data, a memory device arranged to store EDID and the executable instructions and associated data, a number of data ports coupled to the memory device by way of an I2C data bus each coupled to a host device, a method of transferring EDID from the memory device over the I2C data bus to a requesting one of the data ports while servicing a processor memory access request without clock stretching.

Acquisition of extended display identification data (EDID) using inter-IC (I2C) protocol

Managing power in a display controller having an on-board power supply coupled to a host device having an off-board power supply by way of a connector is described. If the on-board power supply is active, then power is supplied to the display controller by the off-board power supply by way of the connector and a low frequency clock arranged to provide a low frequency clock signal is turned on. Alternatively, when it is determined that the on-board power supply is active, then power is supplied to the display controller by the on-board power supply only, the low frequency clock is turned off and a high frequency clock arranged to provide a high frequency clock signal is turned on.

Power management in a display controller

Keys (e.g., decryption key, authentication key) are stored in a non-volatile memory of a display unit. The keys are retrieved in encrypted form into an integrated circuit. The integrated circuit decrypts the keys and uses the keys. As the keys are available in decrypted form only within the integrated circuit and potentially only during use, the keys may not be available to unauthorized third parties.

Display unit storing and using a cryptography key

A video controller having a processor for processing executable instructions and associated data and a number of data ports, a method of acquiring extended display identification data (EDID) by a requesting one of the data ports is described. When on-board power supply is activated, an off-board power supply is deactivated and then the now active on-board power supply provides power to a memory device used to store the EDID and the executable instructions and associated data and to an on-board clock circuit capable of providing a high frequency clock signal. The on-board clock circuit, in turn, provides the high frequency clock signal from the on-board clock circuit to the memory device and if a memory read operation had been in progress when the on-board power supply was activated, then the memory read operation is completed.

Acquisition of extended display identification data (EDID) in a display controller in a power up mode from a power down mode

A computer system includes a host processor, a system memory, a display unit, a pointer device, a VGA controller, and a display memory. The VGA controller communicates with the display memory through an 8-byte wide data bus such that each byte is controlled by a separate column address strobe. To perform a BitBLT operation on a monochrome pattern to be logically combined with 888-RGB color-space formatted data in the display memory, the VGA controller includes a BitBLT control for generating numerous control signals; a color expand circuit for generating in response to such control signals, an 8-byte wide pattern of 888-RGB color-space formatted foreground color data; a circuit for logically combining in response to such control signals, the 8-byte wide pattern of 888-RGB color-space formatted foreground color data and a corresponding 8-byte wide pattern of 888-RGB color-space data received from the 8-byte wide data bus; a bit align circuit for generating in response to such control signals, column address strobe values indicative of bits of the monochrome pattern corresponding to the 8-byte wide pattern of 888-RGB color-space data received from the data bus, by bit aligning the bits of the monochrome pattern; and a memory sequencer for generating in response to such control signals, column address strobe signals corresponding to the values received from the bit align circuit, for strobing into the display memory selected bytes of the logically combined 8-bytes of data.

Technique and apparatus for color expansion into a non-aligned 24 bit

A method and apparatus for improving performance of bit block transfers in display controllers during clipping functions without significantly increasing gate count. In a clipping function, particularly when transferring a portion of a monochrome bit map and color expanding same or in pattern copying, a source start address may not lie on a byte boundary. In order to avoid using time consuming shift left operations in software, the source start address may be adjusted in hardware to an earlier byte boundary. Upon writing data to a destination address, a hardware byte mask may be employed to prevent writing of the additional data retrieved due to the adjustment of the source start address. The source start address and byte mask hardware may be implemented in hardware using bit block transfer engine components and a small amount of additional hardware. The remainder of the clipping functions may remain in software, for example in a display device driver. By eliminating the shift left operations from the software portion of the clipping function, overall system performance is enhanced.

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Danville, CA, United States of America

Ali Noorbakhsh