Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Avago Technologies General IP (singapore) Pte. Ltd.

Clariphy Communications, Inc.

Avago Technologies General IP Pte, Ltd.

Ali Nazemi

Jun Cao

Afshin Momtaz

Siavash Fallahi

Tamer Mohammed Ali

Adesh Garg

Burak Catli

Anand Jitendra Vasani

Mahmoud Reza Ahmadi

Jiawen Zhang

Tim Yee He

Bo Zhang

Delong Cui

Hassan Maarefi

Hyo Gyuem Rhew

Namik Kocaman

Ahmed Elkholy

Meisam Honarvar Nazari

Yousr Ismail

Zhiyu Ru

Lakshmi Rao

Kangmin Hu

Jan Mulder

Jan Roelof Westra

Carl Grace

Ullas Singh

Georgios Asmanis

German Cesar Augusto Luna

Heng Zhang

Seong-Ho Lee

Mahyar Kargar

Kun Chuai

Mohammed Abdul-Latif

Zhi Chao Huang

Wayne Wah-Yuen Wong

Sumant Ramprasad

Ahmadi Mahmoud

Maarefi Hassan

A solution for generating a clock using a quadrature delay can include a first plurality of in-phase (I) inverter pairs configured to output an I signal according to a first input and an inverted in-phase (inverted I) signal according to a second input, with a phase delay circuit coupled in parallel to each of the plurality of pairs. The solution can include a second plurality of quadrature (Q) inverter pairs configured to output a Q signal according to a third clock signal input and an inverted Q signal (inverted Q) according to a fourth clock signal input and a phase detector including a plurality of cells, each of which can receive at least one of the I signal, the inverted I signal, the Q signal or the inverted Q signal and include at least one or more transistors having a gate connected to a ground.

Systems and methods for quadrature delay clock generation

Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.

Systems for and methods of fractional frequency division

A device is provided that includes a counter circuit configured to count cycles of an input clock signal and to generate an output clock signal periodically based on a cycle count of the input clock signal; a multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal; a multiplexer circuit coupled to the multi-phase clock generator and configured to provide a multi-phase clock signal selected from the plurality of multi-phase clock signals to the counter circuit as the input clock signal; and a selection circuit configured to provide a selection signal to the multiplexer circuit periodically to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to a next multi-phase clock signal selected from the plurality of multi-phase clock signals.

Configurable prime number divider using multi-phase clocks

Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.

Quadrature delay locked loops

Systems and methods for data multiplexing include or use a data serializer having a first set of four serializer outputs and a second set of four serializer outputs. The systems and methods also use or include a pair of 4 to 1 multiplexers each having four first multiplexer inputs and one first multiplexer outputs and a 2 to 1 multiplexer having two multiplexer inputs and one multiplexer output.

High-speed transmitter including a multiplexer using multi-phase clocks

A pre-driver circuit includes a differential input circuit to receive a differential-input voltage. A latch circuit can latch voltage levels of output-voltage signals at a differential output port of the pre-driver circuit. A pair of capacitors couple the differential input circuit to the latch circuit. The pre-driver circuit can enable peaking of the output-voltage signals for high-speed operation of the pre-driver circuit and a digital-to-analog converter (DAC)-driver circuit coupled to the pre-driver circuit.

Pre-driver peaking technique for high-speed DACs

A time-interleaved clock circuit, including circuitry to provide multiple clock components of a sampling clock. The clock components are corrected by averaging pairs of the multiple clock components in order to output averaged signals. The time-interleaved clock is applied to data conversion in which input signals of the analog signal domain or of the digital signal domain are sampled based on the corrected clock components and converted to the digital signal domain or the analog signal domain, respectively.

Clock skew suppression for time-interleaved clocks

Multiplexing circuitry and method for driving multiplexing circuits are provided. A circuit includes a multiplexer circuit having symmetrical data input paths driven by a half-rate clock signal and a first stage multiplexing circuit configured to provide input signals to the multiplexer circuit. The first stage multiplexing circuit is driven by quadrature clocks to generate time-shifted data.

Multiplexer circuit for a digital to analog converter

A digital-to-analog converter (DAC) includes a plurality of segments, wherein the plurality of segments includes a first segment electronically coupled to each of the plurality of segments, wherein the first segment includes a predetermined number of most significant bits (MSB), a second segment electronically coupled to each of the plurality of segments, wherein the second segment includes a first predetermined number of least significant bits (LSB), and a third segment electronically coupled with each of the plurality of segments, wherein the third segment includes a second predetermined number of LSBs. Additionally, the DAC includes an all logic implementation.

Multi-segmented all logic DAC

A time-interleaved digital-to-analog converter (DAC) architecture is provided. The DAC architecture includes a multiplexer/encoder configured to receive a data signal and to generate a plurality of data streams based on the data signal. First and second DAC circuits receive respective first and second data streams of the plurality of data streams and selectively process the respective first and second data streams to generate a respective DAC output signal. The respective DAC output signals of the first and second DAC circuits are coupled together to provide an output signal of the DAC architecture.

Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration

A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.

High-speed, low-power reconfigurable voltage-mode DAC-driver

A phase alignment architecture enhances the performance of communication systems. The architecture aligns a divided clock (e.g., in differential Inphase (I) and Quadrature (Q)) to a main clock, even at extremely high speeds, where skew variations of the divided clock are comparable to the main clock period. The improvement in phase alignment facilitates ultra high-speed communications.

Phase alignment architecture for ultra high-speed data path

A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.

Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDes

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Aliso Viejo, CA, United States of America

Ali Nazemi