Intel Corporation

Ali Muhtaroglu

Tawfik Arabi

Greg F Taylor

Kent R Callahan

Bruce Querbach

Mike J Tripp

Amjad M Khan

Michael Bitan

Luis Briceno Guerrero

Marco A Vindas Vargas

Methods and apparatus to provide per die temperature programming for thermally efficient integrated circuit (IC) operation are described. In some embodiments, the junction temperature of an IC component is determined, e.g., to reduce power consumption and/or improve performance. Other embodiments are also described.

Per die temperature programming for thermally efficient integrated circuit (IC) operation

Methods and apparatus to provide per die voltage programming for energy efficient integrated circuit (IC) operation are described. In some embodiments, the voltage potential supplied to an IC component is lowered below a peak performance voltage level, e.g., to reduce power consumption by the component. Other embodiments are also described.

Per die voltage programming for energy efficient integrated circuit (IC) operation

Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate analog behavior. For one embodiment of the invention, a fixed processor ratio is selected and delay statements of the hardware description language correspond to a specific time delay. These fixed values provide the ability to accurately determine and adjust delay in an analog simulation.

Methods and apparatuses for validating AC I/O loopback tests using delay modeling in RTL simulation

An on-die device is provided to measure/detect voltage fluctuations. This may include a control unit to generate differential reference signals (such as differential current signals), a first detector unit and a second detector unit. The differential reference signals may be generated based on a Vcc reference signal and a Vss reference signal. The first detector unit may receive the differential reference signals from the control unit and may receive first voltage signals (also called monitored signals) from a first device under test (DUT) located on the die or from a first area on the die. The first detector unit may provide (or output) a first signal indicative of a voltage fluctuation (voltage droop or overshoot) of the first voltage signals. The second detector unit may receive the differential reference signals from the control unit and may receive second voltage signals (also called monitored signals) from a second device under test (DUT) located on the die. The second detector unit may provide (or output) a second signal indicative of a voltage fluctuation (or voltage droop) of the second voltage signals.

Method and apparatus for on-die voltage fluctuation detection

A set of levels generating circuits, such as a set of digital-to-analog converters, is designed into an integrated circuit on-die. The levels generating circuits apply direct current (DC) voltage levels to on-die sense amplifiers to test sense amplifier trip points for 'input low voltage' (VIL) and 'input high voltage' (VIH). The levels generating circuits are controlled by a set of configuration bits, which may be accessible through the boundary-scan register or the input/output (I/O) loop back pattern generator. The levels generating circuitry allows testing of one number of integrated circuit input pins using a smaller number of input pins.

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Hillsboro, OR, United States of America

Ali Muhtaroglu