Intel Corporation

Tahoe Research, Ltd.

Ali Lehaf

Srinivas V Pietambaram

Steve S Cho

Jung Kyu Han

Robert Alan May

Sri Ranga Sai Boyapati

Hiroki Tanaka

Thomas Heaton

Kristof Darmawikarta

Sashi S Kandanur

Aleksandar Aleksov

Dilan Seneviratne

Ravindranadh T Eluri

Kristof Darmawaikarta

Leonel R Arana

Xiaoying Guo

Kyle Mcelhinny

Onur Ozkan

Alexander Aguinaga

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes an array of bumps to electrically couple the die to the substrate. Each of the bumps have a corresponding base. Different ones of the bases have different widths that vary spatially across the array of bumps.

Methods and apparatus to reduce defects in interconnects between semicondcutor dies and package substrates

Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

Surface finishes with low RBTV for fine and mixed bump pitch architectures

A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

Electromigration resistant and profile consistent contact arrays

Surface finishes with low rBTV for fine and mixed bump pitch architectures

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Chandler, AZ, United States of America

Ali Lehaf