Rambus Inc.

Ali Khoshniat

Ramin Farjadrad

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a wireline signaling link is disclosed. The wireline signaling link includes a first transceiver circuit disposed on a first integrated circuit (IC) chip. The first transceiver circuit includes first transmit circuitry to transmit a first set of symbols representing first data, each symbol having a symbol time. The first transceiver circuit also includes first receiver circuitry to receive a second set of symbols representing second data. A second transceiver circuit is disposed on a second IC chip. The wireline signaling link includes a bidirectional channel having a first end coupled to the first transceiver circuit and a second end coupled to the second transceiver circuit. The wireline signaling link further includes circuitry to make an adjustment of an electrical delay of the wireline signaling link, the adjustment based on a phase relationship between interference associated with the first data that is received by the first receiver circuitry and the second data that is received by the first receiver circuitry.

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San Jose, CA, United States of America

Ali Khoshniat