Intel Corporation

Globalfoundries Inc.

Cypress Semiconductor Corporation

Longitude Flash Memory Solutions Ltd.

Ali Keshavarzi

Vivek K De

Dinesh Somasekhar

Yibin Ye

Muhammad M Khellah

Fabrice Paillet

Stephen H Tang

Shih-Lien L Lu

Siva G Narendra

Shekhar Yeshwant Borkar

Mohsen Alavi

Jaume A Segura

Brian S Doyle

Suman Datta

Tanay Karnik

Krishnaswamy Ramkumar

Gerhard Schrom

Venkatraman Prabhakar

Juanita N Kurtin

Robert S Chau

Igor G Kouznetsov

Arijit Raychowdhury

Ram K Krishnamurthy

James W Tschanz

Jongwook Kye

Yan E Wang

Mahbub Rashed

Suresh Venkatesan

Andy C Wei

Kevin X Zhang

Subramani Kengeri

Krishnamurthy Soumyanath

Fatih Hamzaoglu

Kaushik Roy

Shan Sun

Navneet Jain

Rajendran Nair

Manoj Sachdev

Yunfei Deng

David M Wu

Thurman John Rodgers

Thomas Davenport

David Doman

Timothy L Deeter

Bhaskar P Chatterjee

Janice C Lee

DiaaEldin S Khalil

Gopal Srinivasan

Arman Vassighi

Subi Kengeri

Juanita Kurtlin

Alavi Mohsen

Gary Menezes

Jose L Rossello

A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.

Embedded sonos with triple gate oxide and manufacturing method of the same

A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell has a memory transistor including an angled lightly doped drain (LDD) implant, and a select transistor including a shared source region with a halo implant. The flash memory portion and the EEPROM portion are disposed within one single semiconductor die. Other embodiments are also disclosed.

Bias scheme for word programming in non-volatile memory and inhibit disturb reduction

Embedded SONOS with triple gate oxide and manufacturing method of the same

A microelectronic system including hydrogen barriers and copper pillars for wafer level packaging and method of fabricating the same are provided. Generally, the method includes: forming an insulating hydrogen barrier over a surface of a first chip; exposing at least a portion of an electrical contact electrically coupled to a component in the first chip by removing a portion of the insulating hydrogen barrier, the component including a material susceptible to degradation by hydrogen; forming a conducting hydrogen barrier over at least the exposed portion of the electrical contact; and forming a copper pillar over the conducting hydrogen barrier. In one embodiment, the material susceptible to degradation is lead zirconate titanate (PZT) and the microelectronic systems device is a ferroelectric random access memory including a ferroelectric capacitor with a PZT ferroelectric layer. Other embodiments are also disclosed.

Hydrogen barriers in a copper interconnect process

A method for fabricating a FinFET integrated circuit includes depositing a first polysilicon layer at a first end of a diffusion region and a second polysilicon layer at a second end of the diffusion region; diffusing an n-type material into the diffusion region to form a diffused resistor; and epitaxially growing a silicon material between the first and second polysilicon layers to form fins structures over the diffused resistor and spanning between the first and second polysilicon layers.

Methods for fabricating integrated circuits including semiconductive resistor structures in a FinFET architecture

An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.

Providing timing-closed FinFET designs from planar designs

In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.

Logic circuits using carbon nanotube transistors

Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a channel region on a substrate, wherein the channel region comprises at least one CNT, forming at least one source/drain region adjacent the channel region, and then forming a gate electrode on the channel region, wherein a width of the gate electrode comprises about 50 percent to about 90 percent of a width of the contact region.

Methods of forming carbon nanotube transistors for high speed circuit operation and structures formed thereby

A capacitor includes a substrate (), a first electrically insulating layer () over the substrate, and a fin () including a semiconducting material () over the first electrically insulating layer. A first electrically conducting layer () is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer () is located adjacent to the first electrically conducting layer, and a second electrically conducting layer () is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

Capacitor, method of increasing a capacitance area of same, and system containing same

A Dynamic Random Access Memory (DRAM) cell comprising a leakage compensation circuit. The leakage compensation circuit allows a compensation current from a source to flow to the memory cell storage node of the DRAM cell to compensate the leakage current from the memory cell storage node of the DRAM cell to improve retention time.

Leakage compensation circuit for Dynamic Random Access Memory (DRAM) cells

In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low current levels.

Carbon nanotube fuse element

A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

Asymmetric memory cell

Growing community of inventors

Portland, OR, United States of America

Ali Keshavarzi