Sandisk Technologies Inc.

Sandisk 3D LLC

Other

Advanced Micro Devices Corporation

Ikanos Communications, Inc.

Ali K Al-Shamma

Takao Akaogi

Lee Edward Cleveland

Tz-Yi Liu

Kendra Nguyen

Kenneth K So

Boon Tang Teh

Jin-Lien Lin

Roy E Scheuerlein

Yingchang Chen

Yong K Kim

Yadhu Vamshi Vancha

Luca Giovanni Fasoli

Jeffrey Lee

Kesheng Wang

Nima Mokhlesi

Christopher John Petti

Chang Hua Siau

Seungpil Lee

Grishma Shah

Yoocharn Jeon

Khanh Vinh Nguyen

Farookh Moogat

Kenneth Louie

Dale Smith

James B Hart

Peter Gunadisastra

Jeffrey Koon Yee Lee

Yong Bae Kim

Kapil Verma

John Zhongxuan Zhang

Mong Yang

Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.

Magnetic random-access memory with selector voltage compensation

A sense amplifier for a memory circuit is presented that can sense a selected memory cell in either a first sensing mode, in which current from the selected memory cell flows from the memory cells into the sense amplifier, or a second sensing mode, in which current is discharged from the sense amplifier through the selected memory cell. In the first sensing mode, current from a selected memory cell is conducted through cascaded PMOS transistors to charge a sensing node, with the resultant voltage level on the sensing node used to determine the result of the sensing operation.

Sense amplifier for bidirectional sensing of memory cells of a non-volatile memory

Apparatuses, systems, methods, and computer program products are disclosed for a single pulse memory operation. An electrical source is configured to generate an electrical pulse. A selector for a memory cell is configured to conduct an electrical pulse from an electrical source to a memory cell in response to the electrical pulse exceeding a threshold. A control circuit is configured to maintain at least an operational level for the electrical pulse for a predefined time period to perform an operation on the memory cell.

Single pulse memory operation

A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.

Fast voltage compensation without feedback

One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.

Sensing memory cells using array control lines

Various examples for accelerating multiplication operations are presented, which can be employed in neural network operations, among other applications. In one example, a circuit comprises a non-volatile memory cell, and an input circuit coupled to a gate terminal of the non-volatile memory cell. The input circuit is configured to ramp a control voltage applied to the gate terminal at a ramp rate representing a multiplicand value. An output circuit coupled to an output terminal of the non-volatile memory cell and is configured to generate an output pulse based on the control voltage satisfying a threshold voltage of the non-volatile memory cell, where the output pulse has a duration comprising the multiplicand value multiplied by a multiplier value represented by the threshold voltage.

Neural network matrix multiplication in memory cells

A calibration circuit coupled to a sense amplifier circuit may be configured to determine a response time of the sense amplifier circuit relative to a pulse sequence. Based on the determined response time, the calibration circuit may be configured to set a level of a biasing current to a desired level in order to control the response time of the sense amplifier circuit.

Sense amplifier calibration

A non-volatile memory system includes a plurality of non-volatile memory cells, one or more control circuits that perform programming of the memory cells, a power supply line that provides a supply used to program the memory cells, and a current measurement circuit. The current measurement circuit senses an indication of current on the power supply line. The one or more control circuits determine whether the programming of the memory cells is successful based on the indication of current.

Three dimensional non-volatile memory with current sensing programming status

Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.

Ad hoc digital multi-die polling for peak ICC management

A charge pump system includes a charge pump that receives its clock signals, generated by an oscillator circuit, though a clock buffer. The clock buffer is power-controlled to reduce power consumption and output voltage ripple. The buffer is formed of a series of inverter that are connected to the power supply level through a clamping element, such as a transistor whose gate is controlled by a regulation signal based on feedback from the pump's output.

Charge pump with a power-controlled clock buffer to reduce power consumption and output voltage ripple

A multiple polarity reversible charge pump circuit is disclosed which, in certain embodiments, may be configured to generate a positive voltage at times and may be reversed to generate a negative voltage at other times. Such a charge pump circuit is advantageous if both the positive and negative voltage are not simultaneously required. In certain other embodiments, a charge pump circuit generates a high output current for only a positive boosted voltage in one mode of operation, but lower current positive and negative boosted voltage outputs in another mode of operation. Use with certain erasable memory array technologies is disclosed, particularly certain resistive passive element memory cells, and more particularly in a three-dimensional memory array.

Cooperative charge pump circuit and method

An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array.

Method for using a spatially distributed amplifier circuit

Spatially distributed amplifier circuit

Method for using a multiple polarity reversible charge pump circuit

Growing community of inventors

San Jose, CA, United States of America

Ali K Al-Shamma