Altera Corporation

Alter Corporation

Ali H Burney

Sanjay K Charagulla

Daniel R Mansur

Martin Langhammer

Curt Wortman

Darren Van Wageningen

Boon-Jin Ang

Dan Mansur

Thow-Pang Chong

Chiakang Sung

Khai Nguyen

Nitin Prasad

Yu Xu

Leon Zheng

Jeffrey Tyhach

Kwan Yee Martin Lee

Guy R Schlacter

Kwan Yee Lee

Multiplier circuitry that efficiently utilizes the hard and soft logic regions of a programmable logic device (PLD) is provided. The multiplier circuitry includes a partial product generation block, a compression block (e.g., a carry-save adder), and an carry-propagate adder stage. The partial product generation and compression block are implemented in hard logic while the carry-propagate adder is implemented in soft logic. Local or global routing may be used to connect the hard and soft multiplier components. The multiplier may further include a selectable input register in hard logic and/or a selectable output register in soft logic. This mixed-mode design allows for a substantial savings in the amount of hard logic required to implement the multiplier without a significant decrease in multiplier performance.

Mixed-mode multiplier using hard and soft logic circuitry

Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.

Techniques for optimizing design of a hard intellectual property block for data transmission

Adjustable transceiver circuitry is provided for programmable integrated circuits such as programmable logic device integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The dynamic phase alignment circuit contains a bypassable synchronizer. Four modes of operation are supported by the transceiver circuitry including a normal source synchronous mode, a normal dynamic phase alignment mode, a soft clock data recovery mode, and a phase-locked-loop source synchronous mode. In normal source synchronous mode, the dynamic phase alignment circuit performs no phase alignment or clock rate matching. In normal dynamic phase alignment mode, the dynamic phase alignment circuit performs only phase alignment operations. In soft clock data recovery mode, programmable logic on the programmable integrated circuit is configured to perform rate matching and phase alignment. In phase-locked-loop source synchronous mode, phase alignment and board level deskewing operations are performed.

Programmable logic device integrated circuit with dynamic phase alignment capabilities

Circuitry and methods are provided for control and configuration of a PLD. An embodiment of the invention comprises hard IP circuitry embedded in the PLD. The circuitry may include a gigabit MAC, a hard processor, and a DMA engine. The invention permits a variety of operations, including real-time control and remote programming, without the use of dedicated external circuitry.

Methods and apparatus for control and configuration of programmable logic devices

Integrated circuits such as programmable logic device integrated circuits with memory interface circuitry are provided. The memory interface circuitry measures the timing characteristics of an associated memory during a series of dummy read operations. A multiplexer and phase detector are used to measure phase shifts of memory group clock signals compared to a system clock signal. The memory interface circuitry uses these measurements to adjust a delay-locked-loop circuit. The delay-locked-loop circuit produces a capture clock that is used to read data from the memory.

Memory interface circuitry with phase detection

Programmable logic device integrated circuits are provided that have configurable receivers with dynamic phase alignment capabilities. In situations in which receivers require dynamic phase alignment circuitry, programmable logic elements can be configured to implement a dynamic phase alignment data capture and synchronization circuit. In situations in which dynamic phase alignment receiver circuitry is not required, resources are made available for implementing other user logic. Multiple dynamic phase alignment receiver circuits can share an eight-phase dynamic phase alignment clock signal that is generated by a phase-locked-loop circuit. Switches may be configured to selectively route the dynamic phase alignment clock signal to desired locations on the programmable logic device integrated circuit.

Programmable logic device integrated circuits with configurable dynamic phase alignment circuitry

A circuit includes a sensing circuit, a control circuit, and a programmable delay circuit. The sensing circuit generates delay compensation signals that change in response to variations in at least one of a process and a temperature of the circuit. The control circuit generates dynamic control signals in response to the delay compensation signals. The programmable delay circuit is configurable to delay a signal transmitted through an external terminal of the circuit by a delay that is selected by the dynamic control signals.

Techniques for generating programmable delays

Integrated circuits such as programmable logic device integrated circuits are provided that have resource-efficient receiver circuitry. In source-synchronous system environments, an integrated circuit receives data on multiple buses, each of which has a reference clock signal and associated data signals. One of the reference clocks is provided to a phase-locked-loop circuit, which generates a serial clock and parallel clock for capturing and deserializing data for one of the buses. Each additional bus has an associated phase detector and delay-locked loop in place of a phase-locked loop. The phase detector and delay-locked loop in each additional bus shift the serial clock from the phase-locked loop to produce a serial clock for the additional bus. A parallel clock for each additional bus may be produced using a divider.

Programmable logic device integrated circuit with communications channels having sharing phase-locked-loop circuitry

Input-output circuitry for integrated circuits such as programmable logic device integrated circuits is provided. The input-output circuitry can be configured to operate in a single-ended data mode or a serializer-deserializer mode using programmable routing circuitry such as programmable multiplexers. In single-ended data mode, data registers in the single-ended input-output circuitry may be used to handle transmitted and received single-ended data. In serializer-deserializer mode, the data registers may be configured to form a shift register. The shift register may be used in a serializer-deserializer circuit. Parallel-to-serial and serial-to-parallel data conversion operations may be performed using the shift register. The serializer-deserializer circuit may be connected to differential input-output circuitry such as a differential transmitter circuit or a differential receiver circuit. The data registers may be configured to operate as positive-edge-triggered or negative-edge-triggered devices.

Serializer-deserializer circuits formed from input-output circuit registers

Adjustable transceiver circuitry is provided for programmable integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The transceiver circuitry supports a phase-locked-loop source synchronous mode that can be used to receive data from transmitting integrated circuits that are clocked with a common clock. Each transmitting integrated circuit transmits a clock and associated data signals over a bus. The transceiver circuitry uses a master-slave architecture. A master dynamic phase alignment circuit in each transceiver receives the clock for that bus and selects a corresponding optimal clock phase to use in receiving input data for the bus from a multiphase clock. The master dynamic phase alignment circuit in each transceiver distributes the optimal clock phase to associated slave dynamic phase alignment circuits. Only a single phase-locked loop circuit is need to generate the multiphase clock.

Programmable logic device integrated circuit with dynamic phase alignment capabilities and shared phase-locked-loop circuitry

A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O bank type are compatible within the same programmable device and between different types of programmable devices. The largest size I/O bank type and intermediate size I/O bank types are adapted to be a compatible supersets of every smaller I/O bank type. Support pins are regularly distributed between data pins in each I/O bank type. Multiple instances of the same or compatible I/O banks are arranged to be accessible from different sides of the programmable device. To facilitate circuit board layout, each I/O bank is arranged as a mirror and/or rotation of other I/O banks on the device.

Modular I/O bank architecture

An interface receiver, which is part of an interface that allows the transfer of data between two incompatible I/O standards, includes a crossbar and a barrel shifter that can be implemented using multiplier-accumulator blocks. The crossbar reorders an incoming burst of data and writes the data into a larger data column where the data is barrel-shifted using multiplier-accumulator blocks and transferred out of the receiver when an end-of-packet is detected or the shifted data column as seen from outside the interface receiver is full.

Implementing crossbars and barrel shifters using multiplier-accumulator blocks

A method and system using a delay-locked loop (DLL) to provide multiple phase locked outputs in discrete phase intervals is disclosed. In one embodiment, a reference clock signal is transmitted through a delay chain having a plurality of delay elements. The delay chain is capable of generating a plurality of output clock signals from the reference clock signal. Each of the output clock signals are delayed in discrete phase shift intervals with respect the delay elements. A first of the output clock signals and the reference clock signal are coupled to a first phase comparator capable of forming a first DLL with the delay chain. A second of the output clock signals and the reference clock signal are coupled to a second phase comparator capable of forming a second DLL with the delay chain. The output clock signal from the first DLL or the second DLL may be programmatically selected.

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Fremont, CA, United States of America

Ali H Burney