Pacesetter, Inc.

Micron Technology Incorporated

Siemens-pacesetter, Inc.

Raytheon Company

Aptina Imaging Corporation

Linfinity Microelectronics

Ali Enayat Zadeh

Gene A Bornzin

Wayne A Morgan

Alan B Vogel

Eric J Beuville

Lin Ping Ang

George I Isaac

Joshua J Cantrell

Dro Darbidian

Jonathan A Kleks

Raymond J Wilson

Ashirwad Bahukhandi

Yung-I Chang

Pezhman Amini

A digital unit-cell included in an imaging system includes a light sensor configured to generate an electrical charge in response to receiving light, and an energy storage circuit configured to establish a first parasitic capacitance and second large capacitance to store the electrical charge. The digital unit-cell further includes a gain selection circuit and a dual-mode comparator. The gain selection circuit is configured operate in a first mode to invoke the first capacitance and a second mode to invoke the second capacitance. The dual-mode comparator is configured to operate in a first reset mode that generates a first reset signal having a first pulse duration and a second reset mode that generates a second reset signal having a second pulse duration that is a longer than the first pulse duration.

Pulse-frequency modulation (PFM) digital pixel unit-cell including dual-mode gain selection

A class AB amplifier includes an input stage having a pair of differential input terminals, first and second differential output terminals, and a local common mode feedback circuit. The input stage includes a local common mode feedback circuit having cascode transistor to achieve relatively high gain. The amplifier also includes an output stage having first and second pairs complementary transistors coupled between first and second power supply nodes. One of the complementary transistors in each pair has a gate coupled to the first and second differential output terminals, respectively. The output stage includes a pair of cascode transistor connected to one of the pairs of complementary output transistors. The amplifier can be used to supply a bias voltage to a highly capacitive load, such as voltage sampling capacitors in a CMOS imager.

Class AB amplifier and imagers and systems using same

The various embodiments disclose capacitor multiplier circuits that may be integrated into imaging devices, such as for semiconductor Complimentary Metal Oxide Semiconductor (CMOS) image sensors, to create an effective capacitance in response to a low frequency, such as row-wise temporal noise, that may be generated along a row of image sensor pixels. The created effective capacitance from any one of the capacitor multiplier circuits along with a small signal resistance created by a trans-conductance of a current biasing transistor form a low pass filter that will attenuate the low frequency noise.

Capacitor multipler circuits and the applications thereof to attenuate row-wise temporal noise in image sensors

A master bias current generating circuit includes a current source, a first reference leg, and a second reference leg. The first reference leg includes a first transistor having a first size parameter coupled to the current source and a first diode having a second size parameter coupled to the first transistor. The second reference leg includes a second transistor having a third size parameter less than the first size parameter coupled to the current source and a second diode having a fourth size parameter greater than the second size parameter coupled to the second transistor.

Master bias current generating circuit with decreased sensitivity to silicon process variation

A pipelined analog-to-digital converter features an amplifier block that includes a switching network to implement a double sampling and double conversion principle of operation. The amplifier block utilizes both phases of a clock for sampling and conversion. Additionally, each stage of the analog-to-digital converter is associated with two independent processing blocks. The analog-to-digital converter can achieve double throughput for approximately the same level of power consumption. Alternatively, throughput may be maintained, but the gain-bandwidth of the amplifier block may be reduced by half, thereby halving the DC bias current consumed by the amplifier. Additionally, the output signal of the amplifier itself is not reset to a common mode voltage.

Double throughput analog to digital converter

A circuit within an implantable cardiac stimulation device monitors impedance of an electrode configuration including first and second electrodes in electrical contact with a heart. The circuit is within the implantable cardiac stimulation device which applies stimulation pulses having a current and a voltage magnitude across the electrode configuration. The circuit that monitors impedance of an electrode configuration provides an impedance digital output proportional to the ratio of a stimulation pulse voltage and current.

Implantable cardiac device having an impedance monitoring circuit and method

A linear voltage regulator, such as a low-dropout regulator, supplies power to one or more digital circuits within a computer system. The low-dropout regulator provides a substantially constant output voltage independent of loading conditions. The low-dropout regulator is biased at a relatively low operating current for steady-state operation to improve power efficiency of the low-dropout regulator. During a loading condition change, an adaptive biasing circuit senses the loading condition change and provides additional biasing current to momentarily increase the operating current of the low-dropout regulator to improve transient response.

Linear voltage regulator using adaptive biasing

Methods and apparatus are provided for classifying cardiac events with an implantable cardiac device. Cardiac signals are stored in a buffer. When a significant cardiac event is confirmed, a corresponding segment of the stored cardiac signals is processed to generate a set of feature values. The set of feature values is compared to various sets of reference values. Each set of reference values preferably corresponds to a separate type of cardiac event, so that the cardiac device may classify the significant cardiac event by matching its set of feature values to a set of reference values. Feature values include the maximum positive and negative slew rates exhibited by the cardiac signal during the segment, the maximum positive and negative signal amplitudes, the times to reach the maximum positive and negative signal amplitudes, the area under the cardiac signal curve, the area under the cardiac signal curve above zero as compared to the area below zero, and the number of zero crossings made by the cardiac signal. Additional feature values are generated by simultaneously processing the cardiac signals measured along two different vector directions in the heart.

Methods and apparatus for classifying cardiac events with an implantable

An improved apparatus and method are described for providing a measurement of the charge depleted from a battery used in an implantable device such as a cardiac pacemaker. The measurement is provided not by measuring the voltage level or impedance of the battery, but rather by continuously measuring the electrical current drawn from the battery and integrating that measured current over an integration time period. A precision current-sensing resistor provides a sense signal having a voltage that varies according to the magnitude of current being drawn, and this sense signal is integrated using a voltage-controlled oscillator circuit and counter, which are implemented using CMOS circuitry arranged in a switched-capacitor topology.

Meter for measuring battery charge delivered in an implantable device

An implantable stimulation device has a sensing amplifier circuit for amplifying low amplitude cardiac signals, while maintaining low power, to produce an output signal having a low noise level. The sense amplifier circuit includes a two-stage amplifier, a bandpass filter, and a threshold detector. The first stage comprises a linear differential amplifier which has low gain, good common mode rejection, and a current consumption proportional to the gain. The second stage is a switched-capacitor amplifier which has a programmable gain and low current consumption. The noise content of the system is low and produced substantially entirely in the switched-capacitor amplifier.

Implantable stimulation device having a low noise, low power, precision

A low-power band-pass filter for use in a cardiac pacer includes a single operational amplifier connected in circuit relationship with a plurality of switched capacitors that function as bilinear resistors. Each bilinear resistor comprises a switch for coupling a first lead of a capacitive element to a first terminal and for coupling a second lead of the capacitive element to a second terminal in response to a first state of a control signal, and for coupling the first lead of the capacitive element to the second terminal and for coupling the second lead of the capacitive element to the first terminal in response to a second state of the control signal. Thus, the bilinear resistor switches or oscillates the electrical orientation of the capacitive element between the first terminal and the second terminal in response to the first and second states of the control signal. The invention also includes a method of operating such an implantable filter circuit. Such method includes the steps of: (a) oscillating periodically the electrical orientation of the capacitive element of each bilinear resistor in a prescribed manner; while (b) applying an input signal to the band-pass filter circuit while such oscillation occurs.

Band-pass filter for use in a sense amplifier of an implantable cardiac

A sense amplifier adapted for use with a cardiac pacer or the like includes a constant gain filter, a window comparator circuit and a programmable threshold reference generator circuit. The reference generator circuit generates a programmable window (reference) voltage used by the window comparator circuit to determine whether an input signal, amplified by the constant gain filter, exceeds the window voltage. The reference generator circuit is based on a bipolar junction device having an adjustable emitter area through which a constant current flows. The emitter area is adjusted in response to a control signal. As the emitter area changes as controlled by the control signal, the voltage across the device changes. In a preferred embodiment, a parallel combination or network of switched bipolar junction devices is used to realize the adjustable emitter area. The bipolar junction devices are switched into and out of operation in response to the control signal, thereby increasing or decreasing the net emitter area of the network. When the constant current flows through the network, a precisely controlled adjustable reference voltage is thus generated as a function of the net emitter area.

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Sierra Madre, CA, United States of America

Ali Enayat Zadeh