University of Utah Research Foundation

Intel Corporation

Ali Azam

Jeffrey S Walling

Zhidong Bai

Ashoke Ravi

Wen Yuan

Ofir Degani

Benjamin Jann

Wayne Ballantyne

LiChung Chang

Bassam Khamaisi

A power amplifier circuit including a plurality of analog power amplifiers configured to generate a output power for an output signal; at least one processor configured to: select a highest output power signal; determine an input signal power of a modulated signal; determine an output signal power based on the input signal power; compare the output signal power and the highest output power; and disable a subset of the plurality of analog power amplifiers based on the comparison, wherein a remainder of the plurality of analog power amplifiers are configured to generate the output signal power.

Methods and devices for increased efficiency in linear power amplifier

A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.

Methods and devices for digital clock multiplication of a clock to generate a high frequency output

A switched capacitor digital power amplifier (DPA) or a digital-to-analog converter (DAC) is disclosed. The DPA/DAC includes a plurality of switched capacitor cells connected in parallel. Each switched capacitor cell includes a capacitor and a switch. The switch selectively drives the capacitor in response to an input digital codeword. The switched capacitor cells are divided into sub-arrays and a series capacitor is inserted in series between two adjacent sub-arrays of switched capacitor cells. All the sub-arrays of switched capacitor cells may be in a unary-coded structure. Alternatively, at least one of the sub-arrays may be in a C-2C structure and at least one another sub-array may be in a unary-coded structure. The switch in the switched capacitor cells is driven by a local oscillator signal, and a phase correction buffer may be added for adjusting a delay of the local oscillator signal supplied to sub-arrays of switched capacitor cells.

Switched capacitor radio frequency digital power amplifier and radio frequency digital-to-analog converter

Embodiments of the disclosure are drawn to apparatuses a hybrid switched capacitor array power amplifier (H-SCPA). The H-SCPA may have an array of storage elements divided into sub-arrays. A first sub-array may be configured to receive a delta sigma modulated (DSM) signal. A second sub-array may be configured to receive a Nyquist-rate signal. The H-SCPA may provide an output based on the received DSM and Nyquist-rate signals. The first sub-array and second sub-array may have different architectures. The DSM signal may represent the least significant bits of the signal and the Nyquist-rate signal may represent the most significant bits of the signal.

Apparatuses and methods for hybrid switched capacitor array power amplifiers

Embodiments of the disclosure are drawn to a low-voltage temperature sensor. The temperature sensor may include a waveform generator, a complementary-to-absolute-temperature (CTAT) voltage generator, a voltage reference, two comparators, and digital logic. A waveform of the waveform generator may be compared to both the CTAT voltage and the voltage reference. The output of the comparison of the CTAT and the waveform may be a pulse-width modulated signal that is temperature-dependent. The output of the comparison of the voltage reference and the waveform may be a signal with constant pulse width. The digital logic may receive the pulsed signals and take a ratio of the two signals to determine a temperature.

Temperature sensors and methods of use

Embodiments of the disclosure are drawn to apparatuses and methods for a tunable digital power amplifier (DPA). The tunable DPA may be coupled to a reconfigurable capacitor to form a frequency tunable DPA. The capacitance of the reconfigurable capacitor may be adjusted to optimize the DPA to operate at a desired frequency band. The single tunable DPA may operate over a wide range of frequencies.

Apparatuses and methods for tunable digital power amplifiers

Embodiments of the disclosure are drawn to apparatuses and methods for transmission beamforming. A multiphase beam steering transmitter may include a transmitter array of multiple transmitters. A transmitter may include a multiphase logic decoder that directly controls a power amplifier to perform a vector addition of a beam phase and amplitude. A transmitter of the array may include a multiphase clock generator that outputs basis phases with embedded phase modulation data which are output to the multiphase logic decoder. The multiphase clock generator may receive a modulated clock signal. The PA may be a multiphase switched capacitor power amplifier. The multiphase logic decoder may output two phases adjacent to a desired phase as inputs to clocks of the SCPA. The multiphase logic decoder may further output a control signal that determines which cells in the SCPA are activated and when.

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Salt Lake City, UT, United States of America

Ali Azam