Altera Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Ali Atesoglu

Weiqi Ding

Sergey Yuryevich Shumarayev

Wilson Wong

Sharat Babu Ippili

Allen K Chan

A device includes an inductive-capacitive voltage controlled oscillator (LC-VCO) having a tank circuit and programmable tail current, and a control circuit configured to adjust the tail current based on an amount of capacitance provided to the tank circuit.

Inductive-capacitive (LC) voltage controlled oscillator (VCO) having tuning range controlled by a digital-to-analog converter (DAC) with programmable tail current

Integrated circuits having analog-to-digital converters are provided. Analog-to-digital converters may contain latched comparators. A latched comparator may include inputs configured to receive a differential input voltage signal, a differential reference voltage signal, and a clock signal. The comparator may include a preamplifier, a latching circuit, a level shifter, and a flip-flop coupled in series. The preamplifier may include large input transistors for minimizing offset, stacked tail transistors, and diode-connected load transistors for minimizing kickback noise. The preamplifier may be used to generate amplified voltage signals. The latching circuit may include a first pair of cross-coupled pull-down transistors, a second pair of cross-coupled pull-up transistors, and precharge transistors. The precharge transistors may serve to precharge the latch output to a predetermined voltage level during a first clock phase, whereas the first and second transistor pairs may serve to perform exponential regeneration on the amplified voltage signals during a second clock phase.

Latched comparator circuitry

A divide-by-1.5 circuit includes a divide-by-3 circuit that and a frequency doubler circuit. The divide-by-3 circuit has few logic elements and provides glitch-free operation with a 50 percent duty cycle output. The frequency doubler circuit is based on phase-locked loop circuitry.

High-speed divide-by-1.5 circuit with 50 percent duty cycle

Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

Integrated circuits with configurable inductors

Integrated circuits with phase-locked loops are provided. A phase-locked loop may include voltage-controlled-oscillator (VCO) circuitry. The VCO circuitry may include multiple VCO circuits that receive power supply signals from a positive power supply terminal and a ground power supply terminal. Low-pass filters may be connected to the positive and ground power supply terminals to suppress high frequency noise that may be injected through the power supply terminals. The VCO circuitry may be operable in multiple modes. In a given mode, a selected one of the multiple VCO circuits is enabled while disabling the remaining VCO circuits. Switch circuits formed from transmission gates with pull-down transistors may be used to select which VCO circuit is active.

Voltage-controlled-oscillator circuitry with power supply noise rejection

Tuning circuits with a wide tuning range and a method of tuning an integrated circuit (IC) are disclosed. An embodiment of the disclosed circuits includes varactor banks coupled in series. Each of the varactor banks may include multiple variable capacitors coupled in parallel. A control voltage is routed through the series of varactor banks to adjust the frequency range of the tuning circuit. The control voltage can be selectively routed through one or more of the series of varactor banks based on the operating frequency of the tuning circuit. Enable circuits may be used to control how the control voltage is routed to achieve a specific frequency.

Tuning circuit with a wide tuning range

An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.

Techniques for providing option conductors to connect components in an oscillator circuit

Clock data recovery circuitry with a high speed level shifting circuits and methods are disclosed. One embodiment provides clock data recover with a high speed level shifting circuit that uses an input signal to generate two intermediate signals and uses the intermediate signals to generate an output signal such that voltage stress on individual devices within the level shifting circuit is minimized. In one embodiment, the level shifter includes a first driver and second driver coupled in parallel to provide intermediate signals to an output driver. In a particular aspect, individual transistors of the output driver are subject to voltage stresses that are less than the peak-to-peak amplitude of the output signal. In one embodiment, the first driver includes an n-channel metal oxide semiconductor ('NMOS') cascode circuit, the second driver includes a p-channel metal oxide semiconductor ('PMOS') cascode circuit, and the output driver includes a complementary metal oxide conductor (&#x201c;CMOS&#x201d;) inverter stage. In one embodiment, the level shifter is implemented in an integrated circuit characterized by 45-nanometer technology. In another embodiment, the level shifter is implemented in an integrated circuit characterized by 65-nanometer technology.

Clock data recovery with high speed level shift

Level shifting circuits and methods are disclosed. One embodiment provides a high speed level shifting circuit that uses an input signal to generate two intermediate signals and uses the intermediate signals to generate an output signal such that voltage stress on individual devices within the level shifting circuit is minimized. One embodiment includes a first driver and second driver coupled in parallel to provide intermediate signals to an output driver. In a particular aspect, individual transistors of the output driver are subject to voltage stresses that are less than the peak-to-peak amplitude of the output signal. In one embodiment, the first driver includes an n-channel metal oxide semiconductor ('NMOS') cascode circuit, the second driver includes a p-channel metal oxide semiconductor ('PMOS') cascode circuit, and the output driver includes a complementary metal oxide conductor (&#x201c;CMOS&#x201d;) inverter stage. In one embodiment, the level shifter is implemented in an integrated circuit characterized by 45-nanometer technology. In another embodiment, the level shifter is implemented in an integrated circuit characterized by 65-nanometer technology.

High speed level shift

A circuit comprises a programmable voltage regulator and an oscillator. The programmable regulator generates a regulated supply voltage using an input voltage and changes the regulated supply voltage from a first voltage to a second voltage in response to a first control signal. The first and the second voltages are generated using charge from the input voltage. The regulated supply voltage drives the oscillator. The oscillator varies a frequency of a periodic output signal within a frequency range in response to changes in a control voltage. The frequency range of the periodic output signal varies when the first control signal causes the regulated supply voltage to change from the first voltage to the second voltage.

Growing community of inventors

Milpitas, CA, United States of America

Ali Atesoglu