National Semiconductor Corporation

Crosspoint Solutions, LLC

Advanced Micro Devices Corporation

Artisan Components, Inc.

Synopsys, Inc.

Other

Ali A Iranmanesh

Christopher S Blair

Rick C Jerome

Vida Ilderem

Alan G Solheim

George E Ganschow

Madan Biswal

Rajeeva Lahri

Michael J Grubisich

David Edward Bien

John M Pierce

Christopher O Schmidt

Lawrence K Lam

James L Bouknight

Albert M Bergemont

Mammen Thomas

Frank Marazita

Yakov Karpovich

Brian McFarlane

Ronald P Kovacs

Bamdad Bastani

Bancherd DeLong

Tad Davies

Puneet Sawhney

Steve M Leibiger

Method and apparatus are disclosed for protection of a circuit against process-induced electrical discharge. The method includes forming a diode in close proximity to a charge collector structure capable of exhibiting the antenna effect, and connecting the diode to the charge collector structure by means of local interconnect techniques during the intermediate processing steps. Additionally, the diode may be formed beneath a connecting pad to educe or eliminate antenna effect problems without significant loss of a die area.

Method and apparatus for reducing process-induced charge buildup

A highly flexible, heterogeneous architecture for portable, high density, high performance standard cell and gate array applications is disclosed. The architecture is based on the three basic cells and their derivatives, particularly a transmission gate cell, a logic cell, and a drive cell. For gate array implementations, the cells are arranged in a pre-determined regular array format. For standard cell implementations, the arrangement of the cells may be optimized to suit each target logic gate. Optimized transistor sizing is achievable through leaf cells, software sizing, or both.

Cell based array comprising logic, transfer and drive cells

Method and apparatus are disclosed for protection of a circuit against process-induced electrical discharge. The method includes forming a diode in close proximity to a charge collector structure capable of exhibiting the antenna effect, and connecting the diode to the charge collector structure by means of local interconnect techniques during intermediate processing steps. Additionally, the diode may be formed beneath a connecting pad to reduce or eliminate antenna effect problems without significant loss of die area.

Method and apparatus are disclosed for a low power, high density cell based array structure that permits implementation of designs having compute/drive cell ratios of N:1. The improved performance is provided in part by relocating the substrate and well taps within the compute cell, and in at least some instances by removing the well tap from the drive cell. Further, a extra routing track may be provided by not sharing source/drain areas of adjacent drive cells. Still further, a power mesh may be provided which simplifies routing and improves flexibility.

Cell based array having compute drive ratios of N:1

Method and apparatus are disclosed for a low power, high density cell based array structure that permits implementation of designs having compute/drive cell ratios of N:1. The improved performance is provided in part by relocating the substrate and well taps within the compute cell, and in at least some instances by removing the well tap from the drive cell. Further, an extra routing track may be provided by not sharing source/drain areas of adjacent drive cells.

Cell based array having compute/drive ratios of N:1

A bipolar transistor is provided whose emitter surrounds the base. The transistor has in some embodiments a high ratio of the emitter area to the base area and low collector and emitter resistances. Further, a transistor is provided in which a collector contact region is surrounded by the base. Consequently, a low collector resistance is obtained in some embodiments.

Bipolar transistor with extended emitter

Methods for fabrication of bipolar device having high ratio of emitter

The present invention provides for an antifuse in an integrated circuit, which has a stacked antifuse structure on a first interconnection line. The stacked structure has a first programming layer of amorphous silicon on the first interconnection line, a very thin insulating layer of silicon dioxide on the first programming layer, and a second programming layer of amorphous silicon on the very thin oxide layer. A second interconnection line on the second programming layer completes the antifuse which has a low leakage current between the first and second interconnection lines.

Multilayer antifuse with low leakage and method of manufacture therefor

Bipolar transistors

The present invention provides for a method of forming an antifuse in an integrated circuit having a first insulating layer on a semiconductor substrate. The method comprises forming a first metal interconnection layer on the first insulating layer; forming a relatively thin, second insulating layer over the first metal interconnection layer with a via where the antifuse is to be located to expose the first metal interconnection layer; forming first spacer regions on the sidewalls of the second insulating layer; forming a programming layer on the second insulating layer and in the via to contact the first metal interconnection line; forming second spacer regions on the sidewalls of the programming layer in the via; forming a barrier metal layer on the programming layer; forming a relatively thick, third insulating layer on the barrier metal layer with a second aperture to expose a portion of the barrier metal layer; and forming a second metal interconnection layer on the third insulating layer and in the second aperture to contact the portion of the second barrier metal layer. The spacer regions force programming to occur away from the sidewalls of the via for greater uniformity of programming voltages and greater stability on the R.sub.ON resistance. Additionally, the capacitance of the unprogrammed antifuse is reduced.

Antifuse with double via, spacer-defined contact

A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

Method of fabricating BiCMOS device

An antifuse structure in an integrated circuit including a first interconnection line, a second interconnection line formed over the first interconnection line, and a plurality of programming layers between the first and second interconnection lines. Each pair of programming layers has a metal layer therebetween which dissolves with the programming layers to form a conducting link during the programming of such antifuse structure. Such antifuse structure may also include a conductive plug between the programming layers and the second interconnection line.

Method of forming an antifuse in an integrated circuit

A series of self-aligned, intermediate strips of conductive material, which contact each of the drain regions in a corresponding number of columns of drain regions in a flash electrically programmable read-only-memory (EPROM), are formed as a thick layer of planarized polysilicon. By utilizing intermediate strips of conductive material which are formed from a thick layer of polysilicon, the formation of cracks or voids in the intermediate strips of conductive material can be eliminated.

Method of making increased-density flash EPROM that utilizes a series of

The present invention provides for an integrated circuit antifuse structure having a first metal interconnection line, a programing layer over the first interconnection line, an etch stop layer over the programming layer, a sacrificial buffer layer over the etch stop layer, an insulating layer over the buffer layer, and a second metal interconnection line over the insulating layer. An aperture extends through the insulating layer and the buffer layer. The buffer layer has etching characteristics which are different from those of the insulating layer and the etch stop layer. This permits the aperture through the insulating layer to be formed with substantially vertical sides and through the buffer layer to be formed with substantially sloped sides. The second interconnection line extends into the aperture to form an antifuse structure with a low capacitance and a consistent programming voltage.

Low-capacitance, isotropically etched antifuse and method of manufacture

A method and resulting antifuse structure in an integrated circuit include a first metal interconnection layer on a first insulating layer over the substrate of the integrated circuit, a second insulating layer over the first metal interconnection layer. The second insulating layer has a via therein and a programming layer is located in the via. Such programming layer includes a first region on the first metal interconnection layer which is removed from sides of the second insulating layer in the via, and a second region on the sides of the second insulating layer via. The first region has substantially a first thickness, the second region has substantially a second thickness which is greater than the first thickness. Upon programming the antifuse structure, a conducting link forms in the first region of the programming layer.

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Sunnyvale, CA, United States of America

Ali A Iranmanesh