Advanced Micro Devices Corporation

Legerity, Inc.

Cirrus Logic Inc.

Alfredo R Linz

Carlin D Cabler

Glen W Brown

Martin P Soques

Dale E Gulick

Larry David Hewitt

Michael Allan Kost

Terry Lynn Cole

Safdar M Asghar

Paul G Schnizlein

David N Suggs

Geoffrey E Brehmer

David E Norris

Michael E Spak

Jeffrey M Blumenthal

Ryan E Feemster

Michael Hogan

Sahil Singh

David J Guercio

Alan T Torok

John L Melanson

Alan F Hendrickson

Joe W Peterson

Vijayakumaran Velayudhan Nair

Shatam Agarwal

Kan Wang

Velayudhan V Nair

A variable resistance device may be used in a dimmer compatibility circuit to reduce power dissipation in an integrated circuit of the dimmer compatibility circuit. For example, the integrated circuit may include switches coupled to resistors external to the integrated circuit. The integrated circuit may operate the switches to commutate among the external resistors and select a voltage drop that reduces a voltage at a drain voltage of the switches. The reduced drain voltage reduces power dissipation in the switches and instead dissipates the power in the external resistors.

Variable resistance device for reduced power dissipation in dimmer compatibility circuits

A lighting system includes methods and systems to mix colors of light emitted from at least two LED emitters. In at least one embodiment, the lighting system includes a controller that responds to phase-cut angles of the dimming signal and correlates the phase-cut angles with a predetermined black body radiation function to dynamically adjust a color spectra of the mixed light in response to changes in phase cut angles of the phase-cut dimming level signal. In at least one embodiment, the controller utilizes the predetermined black body radiation function to dynamically adjust the color spectra of the mixed, emitted light in response to changes in phase cut angles of a phase-cut dimming level signal. In at least one embodiment, the predetermined black body radiation function specifies correlated color temperatures (CCTs) that model the CCTs of an actual non-LED based lamp, such as an incandescent lamp.

Color mixing of electronic light sources with correlation between phase-cut dimmer angle and predetermined black body radiation function

A lighting system includes one or more methods and systems to control the color spectrum of a lamp in response to both temperature and dim levels. In at least one embodiment, the lighting system includes a controller to control a correlated color temperature (CCT) and intensity of the lamp by independently adjusting currents to electronic light sources based on a dim level of the lighting system and temperature of the lighting system. The controller controls a first current to a first set of LEDs and a second current to a second set of LEDs. The control of the first current by the controller is jointly dependent on a dim level and temperature in the lighting system. In at least one embodiment, the control of the second current is dependent on the dim level or the dim level and temperature.

Color coordination of electronic light sources with dimming and temperature responsiveness

A method and apparatus are provided. The method includes providing an enable signal to a configuration device for generating a preselected signal, providing the preselected signal to a peer station over a subscriber line, and adjusting a transmission path of a signal to the peer station through the subscriber line in response to the preselected signal.

Method and apparatus for verifying and correcting connectivity

A method and apparatus are provided for delivering data within a frame to a peer station, the frame having at least a first and a second symbol. The method comprises determining whether the data in the first symbol is greater than or equal to a coding-gain threshold, loading at least a portion of the data within at least the second symbol in response to determining the data in the first symbol is greater than or equal to the coding-gain threshold to provide a new frame, and transmitting the new frame.

Method for conserving power in transceivers

A method and apparatus are provided for supporting a plurality of user transceivers with a host transceiver. The method includes allocating at least one symbol of a DMT frame to a first user transceiver of the plurality of transceivers, providing a control signal from a second user transceiver of the plurality of transceivers to the host transceiver, allocating at least one symbol of the DMT frame to the second user transceiver in response to the control signal.

Multi-tone transciever for multiple users

A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

Monolithic PC audio circuit

A method and modem is provided for communicating data using a plurality of tones. The modem includes an IFFT unit capable of providing a signal comprising a plurality of tones, an interpolator capable of interpolating the signal to produce an interpolated signal, and a tone adder capable of adding a tone having a first preselected frequency and the interpolated signal to produce an output signal.

Method and apparatus for generating tones in a multi-tone modem

A communication system includes a data sampling rate converter that uses a closed-loop control arrangement to convert an input signal at a first sampling rate to a second, asynchronous, sampling rate without requiring extensive input buffering. A number of data registers in a first-in-first-out input buffer are used to receive and store data samples at the first rate and to pass the data samples from the input buffer at a controlled rate. The input buffer indicates the current capacity of the input buffer circuit for use by a frequency ratio estimation circuit, which is arranged to respond by providing an estimate of the actual ratio between the first rate and the second rate. A control circuit responds to the frequency ratio estimation circuit by generating the controlled rate at which the data samples are to be passed from the input buffer. In this manner, the data samples are passed from the input buffer at the controlled rate for processing and outputting the data at the second rate.

Frequency ratio estimation arrangement and method thereof

A communication system includes a data sampling rate converter that uses a closed-loop control arrangement to convert an input signal at a first sampling rate to a second, asynchronous, sampling rate without requiring extensive output buffering. A small number of data registers in a first-in-first-out output buffer is used to receive and store computed data samples at a controlled rate and to pass these data samples to the output at a second rate. The output buffer indicates, the current capacity of the output buffer for use by a frequency ratio estimator, which is arranged to respond by providing an estimate of the actual ratio between the first rate and the second rate. A controller responds to the frequency ratio estimator by generating the controlled rate at which the computed data samples are to be passed to the output buffer. In this manner, the processed data samples are passed to the output buffer at the controlled rate and are output at the second rate. The processed data use the input samples received at a first rate and the ratio value.

Arrangement for asynchronous decimation using a frequency ratio

A digital noise shaper circuit is provided which includes a signal transfer function and a noise transfer function, with associated coefficients and gain scaling factors, which ensures a predetermined frequency response, signal passband and noise stopband, and which converts a multi-bit digital signal to a 1-bit digital signal.

Fourth order digital noise shaper circuit

A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects

Monolithic PC audio circuit with enhanced digital wavetable audio

A stereo audio CODEC, including means for performing D/A and A/D conversions, means for reducing digitally induced noise during attenuation/gain changes, data format conversion means, analog and digital filtering means, analog mixing means, on-chip 16-sample, 32-bit wide record and playback FIFOs, serial interface with external serial DSP, large local memory for supplementing on-chip record and playback FIFOs, control registers, register data bus and synthesizer DAC.

Stereo audio CODEC

An analog-to-digital conversion circuit is described which includes a front end sigma-delta modulator circuit, a multi-stage digital decimation filter circuit, and a digital compensation filter circuit. An overrange detect circuit is also provided.

Delta-sigma ADC with multi-stage decimation filter and gain compensation

This invention is for a multi-stage digital decimation filter, which includes a sinc.sup.6 filter, a half-band linear phase FIR filter and a symmetric, linear phase, FIR filter and a digital compensation filter. The multi-stage decimation filter down-samples the output of a sigma-delta modulator by a factor of about 64. The compensation filter provides compensation for rolloff introduced by the multi-stage decimation filter.

Growing community of inventors

Austin, TX, United States of America

Alfredo R Linz