Micron Technology Incorporated

Alfredo Palazzo

Luca Porzio

Roberto Izzi

Marco Onorato

Andrea Vigilante

Sean L Manion

Massimo Zucchinali

Bryan D Butler

Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.

Latency reduction of boot procedures for memory systems

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Monza, Italy

Alfredo Palazzo