Ampere Computing LLC

Applied Micro Circuits Corporation

Macom Connictivity Solutions, LLC

Alfred Yeung

Hamid Partovi

Luca Ravezzi

John Ngai

Ronen Cohen

Ojas Dharia

Yan Chong

Russell Homer

Vamsi Srikantam

Abhiram Saligram Chandrashekar

John Gregory Favor

Matthew Ashcraft

Jeremy Plunkett

David S Oliver

Subbayyan Venkatesan

Ronen Cohan

Manoj Kulkarni

Rich Thaik

Subbayyan Venkatsan

April Lambert

Matthew W Ashcraft

A metal-insulator-metal (MIM) capacitor design methodology and system substantially maximizes the benefits of including MIM capacitors in an integrated circuit design while substantially minimizing the negative impacts resulting from increased capacitance. A process analysis is performed on an integrated circuit design to determine a metal layer that is likely to be most adversely affected by the presence of MIM capacitor cells. The MIM capacitor cells are then designed to have specific sizes and orientations based on results of the process analysis, taking the most affected metal layer into consideration. Finally, the MIM capacitor cells are placed at selected locations on the die in an algorithmic fashion in order to satisfy a design target of maximizing coverage area while avoiding interference with signal paths and critical or sensitive components.

MIMCAP creation and utilization methodology

Various aspects provide for mitigating voltage droop associated with a microprocessor (e.g., by controlling a clock associated with the microprocessor). For example, a system can include a microprocessor and a controller. The microprocessor can receive a clock provided by a clock buffer. The controller can control frequency of the clock provided by the clock buffer based on a voltage associated with the microprocessor. In an aspect, the controller can reduce the frequency of the clock in response to a determination that the voltage satisfies a defined criterion. Additionally, the controller can incrementally increase the frequency of the clock in response to another determination that the voltage satisfies another defined criterion after satisfying the defined criterion.

Clock control based on voltage associated with a microprocessor

Techniques efficiently improve circuit design to reduce its sensitivity to random device variation. A characterizer component can identify a subset of cells for an integrated circuit that can be representative of respective other cells of a set of cells. The characterizer component can analyze the representative cells of the subset to generate a variation profile, and can map the representative cells to physical cells used in the design of the circuit. A cell library comprising cells that are usable, have limited usage, and/or have general usage can be generated based on analysis results from the mapped cells. The circuit can be reconstructed based on the list of available cells using the cell library. The reconstructed circuit can be analyzed, and in case of a cell(s) violating a constraint, the cell(s) can be modified or enhanced to achieve target performance criteria.

Efficient techniques for process variation reduction for static timing analysis

Techniques efficiently improve an integrated circuit design by simultaneously analyzing timing paths of the circuit design. A design management component can access data relating to the integrated circuit design from a design database. The design management component can perform a static timing analysis of the integrated circuit design and generate a timing path distribution, filtered analytics, and/or a probability density function associated with the integrated circuit design, wherein all of the timing paths of the integrated circuit design can be evaluated. The design management component can determine a modification to make to a cell, device, interconnection between cells or devices, or another element(s) of the integrated circuit design, based at least in part on the static timing analysis, the timing path distribution, the filtered analytics, and/or the probability density function, to generate a modified integrated circuit design, in accordance with defined design criteria.

Techniques for statistical frequency enhancement of statically timed designs

Various aspects provide for detecting voltage droops. For example, a system can include a voltage calibrator component and a comparator component. The voltage calibrator component can convert a first supply voltage associated with a power distribution network of an integrated circuit to a second supply voltage via a resistance ladder circuit. The comparator component can generate a comparison output signal in response to a determination that a comparison between the second supply voltage and a reference voltage satisfies a defined criterion.

Variation immune on-die voltage droop detector

A self-referenced on-die voltage droop detector generates a reference voltage from the supply voltage of an integrated circuit's power distribution network, and compares this reference voltage to the transient supply voltage in order to detect voltage droops. The detector responds to detected occurrences of voltage droop with low latency by virtue of being located on-die. Also, by generating the reference voltage from the integrated circuit's power domain rather than using a separate reference voltage source, the detector does not introduce noise and distortion associated with a separate power domain.

Self-referenced on-die voltage droop detector

Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with respective word lines and bit lines. A write assist component can be associated with a subset of the memory cells associated with a bit line. Configuration of the write assist component can be based on the type of transistors employed by write circuits associated with the memory cells. During a write operation, the write assist component adds an additional current path to the ground, or the power supply, or both, at or in proximity to the far end of the write bit line when an appropriate write polarity is applied to the bit line by the driver at the other end of the bit line. This mitigates the effects of resistance of the bit line, which mitigates IR loss of the write signal.

Write assist for memories with resistive bit lines

A semiconductor chip allows for a selected amount of on-die decoupling capacitance to be connected to a very-large-scale integrated circuit (VLSI) system after the circuit design is complete. The semiconductor chip comprises an integrated circuit disposed on a packaging substrate, and a power distribution network that is electrically connectable to the integrated circuit via a programmable connectivity array via the packaging substrate.

Package programmable decoupling capacitor array

MIMcap creation and utilization methodology

A decoupling capacitor circuit design facilitates high operational frequency without sacrificing area efficiency. In order to disassociate the sometimes opposing design criteria of high operational frequency and area efficiency, a p-channel field effect transistor (PFET) and an n-channel field effect transistor are connected in a half-cross-coupled (HCC) fashion. The HCC circuit is then supplemented by at least one area efficient capacitance (AEC) device. The half-cross-coupled transistors address the high frequency design requirement, while the AEC device(s) address the high area efficiency requirement. The design eliminates the undesirable trade-off between operating frequency and area efficiency inherent in some conventional DCAP designs.

High efficiency half-cross-coupled decoupling capacitor

A latch device is provided with a driver and a shadow latch. The driver has an input to accept a binary driver input signal, an input to accept a clock signal, and an input to accept a shadow-Q signal. The driver has an output to supply a binary Q signal equal to the inverse of the driver input signal, in response to the driver input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the driver input signal, and an input to accept the clock signal. The shadow latch has an output to supply the shadow-Q signal equal to the inverted Q signal, in response to the driver input signal and clock signal.

Shadow latch

Disclosed herein is a pseudo single-phase flip-flop. The master section includes a pre-dissipation stage and a first keeper. The pre-dissipation stage discharges the first keeper to the mDb second binary value, and selectively charges the first keeper with the mDb first binary value in the master pass mode. The pre-dissipation stage selectively prevents the first keeper from charging to the mDb first binary value in response to one of the clock phases. The slave section includes a pre-charge stage, a second keeper, a post-dissipation stage, and a third keeper. The second keeper maintains a first binary value in a slave pass mode when the mDb signal has a second binary value. The second keeper supports the second binary value in the slave pass mode when the mDb signal has the first binary value. The third keeper maintains the Q signal binary value during the slave hold mode.

Pseudo single-phase flip-flop (PSP-FF)

A latch device is provided with a relay and a shadow latch. The relay has an input to accept a binary relay input signal, an input to accept a clock signal, an input to accept a shadow-Q signal, and an output to supply a binary Q signal value equal to the relay input signal value. The relay output is supplied in response to the relay input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the relay input signal, an input to accept the clock signal, and an output to supply the shadow-Q signal with a value equal to an inverted Q signal value. The shadow latch output is supplied in response to the relay input signal and clock signal.

Pass gate shadow latch

A hazard-free minimal-latency flip-flop (HFML-FF) is provided. A master latch includes an input to accept a Dsignal, an input to accept a clock signal, an input to accept an inverted shadow-Dsignal, and an output to supply a Dsignal. The master latch has an input to accept a shadow-Dsignal, an input to accept the clock signal, and an output to supply a shadow-Dsignal and the inverted shadow-Dsignal. The slave latch has an input to accept the Dsignal, an input to accept the clock signal, an input to accept an inverted shadow-Q signal, and an output to supply a Q signal. The slave latch has an input to accept either the Dsignal or the shadow-Dsignal, an input to accept the clock signal, and an output to supply a shadow-Q signal and the inverted shadow-Q signal. The design may use clocked inverters or pass gates.

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Alfred Yeung