Cisco Technology, Inc.

Vlsi Technology, Inc.

Siemens Business Communication Systems, Inc.

Alfred Platt

Kent Wayne Wendorf

Neufito L Fernandes

Simon Kwong

Kenneth J Duda

A system and method for testing the random access memory of a computer system is disclosed. A memory-testing engine is embedded in the utility bus controller of an application specific integrated circuit, which is coupled to a random access memory in need of testing. Upon receiving an initiation signal over a bus from the central processing unit, the memory-testing engine begins writing data to a targeted area of the memory, and then reading back the stored data and comparing the data to what was sent. Having the memory-testing engine distributed to the memory's being tested allows several memory devices to be tested simultaneously.

System and method to asynchronously test RAMs

A machine and method for allowing a simulated processor environment to interact with a simulated digital environment to simulate a processor-based system. Embodiments of the present invention contemplate that interaction between the processor environment and digital environment can be implemented by providing the processor environment with a list of 'significant events' (e.g., reads and writes) that are pertinent to the digital environment. Embodiments of the present invention also contemplate that the processor environment and digital environment can be synchronized by allowing operations to occur on either the processor environment or the digital environment, but not on both simultaneously.

Machine and method for simulating a processor-based digital system

An apparatus and method for providing a built-in self-test functional system block (BIST FSB) for self-testing a network interface integrated circuit having a Universal Test & Operations PHYInterface for ATM (UTOPIA) interface. The BIST FSB includes a random number generator, a signature analyzer, two cell counters, and a state machine for controlling the BIST FSB. Means are provided for looping the transmitter of the network interface integrated circuit back to the receiver of the network interface integrated circuit. When the BIST test is started, the state machine waits until the receiver is synchronized. Then user cells are generated and fed to the transmitter for the network interface integrated circuit. At the same time, cells on the receive side are collected and compressed into a signature. When all of the cells have been received, the signature is compared with a precalculated signature. If the signatures match, the test is passed. The BIST FSB in its self-test mode disables user data from entering the network interface integrated circuit and inserts its own data from a random number generator. The BIST monitors data going from the network interface integrated circuit receiver back to BIST. This data is 'compressed' into one number and compared with a predetermined signature in a signature analyzer.

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Cupertino, CA, United States of America

Alfred Platt