Cova Technologies, Inc.

Micron Technology Incorporated

Other

Inmos Limited

Ramtron Corporation

Alfred P Gnadinger

Klaus Dimmler

Gary F Derbenwick

Matthew Hanson

Stefan Linder

William Dennis Ryden

Carlos P De Araujo

David I Dalton

James R Adams

Ross Lyndon-James

Donald L Black

A nonvolatile semiconductor memory device is described where each memory cell is composed of a single field effect transistor with a dual gate dielectric comprising a dielectric interfacial layer in contact with a silicon substrate and a ferroelectric layer in between the interfacial layer and the gate electrode. To program (write) the cell the ferroelectric layer is polarized in one of two directions, the ferroelectric polarization creating a large electric field in the interfacial layer. This electric field causes electrons or holes to be transported across the interfacial layer and be trapped in the ferroelectric layer establishing a high (erased) or low (programmed) threshold voltage depending on the direction of the ferroelectric polarization representing the two logic states. To read the memory cell a voltage is applied to the drain of the selected transistor and depending on whether a high or low threshold state was programmed into the cell a low or high current is sensed.

Single transistor charge transfer random access memory

A method of storing and accessing two data bits in a single ferroelectric FET includes selectively polarizing two distinct ferroelectric regions in the same gate dielectric layer separated by a non-ferroelectric dielectric region. A first ferroelectric region is sandwiched between the substrate and the gate terminal in the region of the source and is polarized in one of two states to form a first data bit within the FET. A second ferroelectric region is sandwiched between the substrate and the gate terminal in the region of the drain and is polarized in one of two states to form a second data bit within the FET. Detection of the first data bit is accomplished by selectively applying a read bias to the FET terminals, a first current resulting when a first state is stored and a second current resulting when a second state is stored. The polarization of the second data bit is accomplished by reversing the source and drain voltages.

Ferroelectric transistor for storing two data bits

A single transistor ('1T') ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric. The memory cell of the present invention comprises a substrate, an overlying ferroelectric layer, which may comprise a film of rare earth manganite, and an interfacial oxide layer intermediate the substrate and the ferroelectric layer. In a preferred embodiment, the ferroelectric material utilized in an implementation of the present invention may be deposited by metallorganic chemical vapor deposition ('MOCVD') or other techniques and exhibits a low relative dielectric permittivity of around 10 and forms an interfacial layer with a relative dielectric permittivity larger than that of SiO, which makes it particularly suitable for a 1T cell.

Single transistor ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric

Data retention of a ferroelectric transistor is extended by intecting holes or electrons into the ferroelectric transistor when power is removed. The ferroelectric FET has a mechanism to trap charge in a buffer dielectric layer or in the ferroelectric layer sandwiched between a top electrode and a silicon substrate. The state of polarization is detected before power is removed from the ferroelectric FET. Charge is injected into the ferroelectric FET to produce a first threshold voltage when a first polarization state is determined before power is removed. Charge is removed from the ferroelectric FET to produce a second threshold voltage when a second polarization state is determined before power is removed. When the ferroelectric FET is powered up again, the state of charge injected is determined. The ferroelectric FET is then polarized to correspond to a first threshold voltage when the charge state corresponding to the first threshold is determined. The ferroelectric FET is polarized to correspond to a second threshold voltage when a charge state corresponding to the second threshold is determined.

Ferroelectric transistor with enhanced data retention

Data retention of a ferroelectric transistor is extended by injecting holes or electrons into the ferroelectric transistor when power is removed. The ferroelectric FET has a mechanism to trap charge in a buffer dielectric layer or in the ferroelectric layer sandwiched between a top electrode and a silicon substrate. The state of polarization is detected before power is removed from the ferroelectric FET. Charge is injected into the ferroelectric FET to produce a first threshold voltage when a first polarization state is determined before power is removed. Charge is removed from the ferroelectric FET to produce a second threshold voltage when a second polarization state is determined before power is removed. When the ferroelectric FET is powered up again, the state of charge injected is determined. The ferroelectric FET is then polarized to correspond to a first threshold voltage when the charge state corresponding to the first threshold is determined. The ferroelectric FET is polarized to correspond to a second threshold voltage when a charge state corresponding to the second threshold is determined.

A single transistor (&ldquo;1T&rdquo;) ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric. The memory cell of the present invention comprises a substrate, an overlying ferroelectric layer, which may comprise a film of rare earth manganite, and an interfacial oxide layer intermediate the substrate and the ferroelectric layer. In a preferred embodiment, the ferroelectric material utilized in an implementation of the present invention may be deposited by metallorganic chemical vapor deposition (&ldquo;MOCVD&rdquo;) or other techniques and exhibits a low relative dielectric permittivity of around 10 and forms an interfacial layer with a relative dielectric permittivity larger than that of SiO , which makes it particularly suitable for a 1T cell.

A radio frequency identification device (RFID) has an antenna formed on a chip. The chip has backside and a front side coated with conductive traces, which are connected through conductive traces on the sides of two elongate through-hole slots formed on the chip to form an operative coil having the chip as a core. In one embodiment, the antenna chip may be stacked above an integrated circuit. In another embodiment, the integrated circuit may be formed on the antenna chip. The antenna chip may include a high magnetic permeability layer to increase the inductance of the coil, a capacitor to tune the coil to a desired frequency, and a coupling capacitor to power the integrated circuit. As well as the specific application disclosed, an inductance useful in numerous applications can be formed according to the above structure.

Radio frequency identification transponder having integrated antenna

Problems arise when connecting the bottom plate of a ferroelectric capacitor to the source of its associated access transistor during the fabrication of an ultra large scale integrated memory circuit. The temperature and ambient of certain steps of the fabrication process adversely affects ohmic properties of the connection. To overcome these problems, an insulative layer is formed between the bottom plate of a ferroelectric capacitor and its associated transistor. The insulative layer separates the source from the bottom electrode, and subsequent high temperature swings during the remainder of the fabrication process do not produce any direct connection between the source and the bottom plate. After the memory circuits have been fabricated on the semiconductor wafer, a voltage is applied across the ferroelectric capacitor and the insulative layer, preferably during a wafer probe. The magnitude of the applied voltage is selected to breakdown the insulative layer, but does not damage the ferroelectric layer. As a result, a good ohmic contact is produced between the bottom plate and the source of its associated transistor.

Method of making a ferroelectric capacitor and forming local interconnect

A solid-state memory unit is constructed using stacked wafers containing a large number of memory units in each wafer. Vertical connections between wafers are created using bumps at the contact points and metal in through-holes aligned with the bumps. The bumps on one wafer make contact with metal pads on a mating wafer. Mechanical bonding between the bumps and mating metal pads on another wafer is preferably avoided so that fractures due to thermal expansion differentials will be prevented. Serial addressing and data access is employed for the memory units to minimize the number of connections needed. Also, the metal pads, through-holes and bumps are formed at corners of the die and thus shared with adjacent units whenever possible, further reducing the number of vertical connections.

High density data storage using stacked wafers

Ferroelectric capacitor and method for forming local interconnect

A wristwatch contains communication and memory circuitry and a transmitter. The memory circuit stores a personal identification number of a single user. The communication and memory circuitry is driven by the same battery which powers the timekeeping structure of the watch. A transmitter transmits data from the reader to the wristwatch, placed proximate thereto. The reader has a keypad by which the user can enter a personal identification number, and the watch compares the transmitted number to the user-entered number. If the numbers match, a transaction may occur.

Timepiece communication system

The invented technique permits the gate length to equal the channel length: source/drain regions are self-aligned and non-overlapping with respect to their gate electrode. The non-overlapping feature, along with other optimized device characteristics, are generally provided by defining a gate electrode over a substrate, forming an implant mask of dielectric, for example, on the sides of the gate electrode, and implanting a source/drain region such that the implant mask shields a portion of the substrate from implantation to provide a gap between a side edge of the gate electrode and the implanted regions. The source/drain region is then heat driven until its side edge is substantially aligned with the edge of the gate electrode. Self-aligned source/drain contacts are also provided using the implant mask to isolate the gate electrode from the contacts and interconnects.

Growing community of inventors

Colorado Springs, CO, United States of America

Alfred P Gnadinger